I’m trying to write a 2-bit up counter in Verilog and it must have dff in it’s design. But, when I test it out puts are = xx. Can you please help me to fix it?
module dff(d,clk,q);
input d,clk;
output reg q;
always @(posedge clk ) begin
q <=d;
end
endmodule
module sequence_counter (
input clk,
output reg [1:0]sequence
);
wire [1:0]a;
dff d0(.d(~a[0]) , .clk(clk) , .q(a[0]));
dff d1(.d(a[1]^ a[0]) , .clk(clk) , .q(a[1]));
always @(posedge clk) begin
sequence = a;
end
endmodule
and this is the testbench :
`timescale 1ns / 1ns
module tb;
reg clk;
wire reg [1:0] out_sequence;
sequence_counter uut_sequence(.clk(clk) , .sequence(out_sequence));
initial begin
clk = 0;
$display("Initial state at time=%0t, sequence_out =%b", $time, out_sequence);
#10 $display("Initial state at time=%0t, sequence_out =%b", $time, out_sequence);
#10 $display("Initial state at time=%0t, sequence_out =%b", $time, out_sequence);
#10 $display("Initial state at time=%0t, sequence_out =%b", $time, out_sequence);
#10 $display("Initial state at time=%0t, sequence_out =%b", $time, out_sequence);
#10 $display("Initial state at time=%0t, sequence_out =%b", $time, out_sequence);
$finish;
end
// Clock generation for sequence_counter
always #5 clk = ~clk;
endmodule
the output I get is this:
Initial state at time=0, sequence_out =xx
Initial state at time=10, sequence_out =xx
Initial state at time=20, sequence_out =xx
Initial state at time=30, sequence_out =xx
Initial state at time=40, sequence_out =xx
Initial state at time=50, sequence_out =xx
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The quickest fix is to initialized q in the dff module:
output reg q=0;
This eliminates the unknown (x) values:
Initial state at time=10, sequence_out =00
Initial state at time=20, sequence_out =01
Initial state at time=30, sequence_out =10
Initial state at time=40, sequence_out =11
Initial state at time=50, sequence_out =00
It would be better to model a counter using standard behavioral code, instead of instantiating flip-flops. Alternately, you should use a reset input signal to reset all the logic.