I have this code

module System (
    input CLK,

    inout [15:0] bus_ROM_data,
    inout [15:0] bus_ROM_addr,
    input bus_ROM_write,
    input bus_ROM_cs,  // 1 = shell owns the bus

    inout [15:0] bus_RAM_addr,
    input bus_RAM_write,
    input bus_RAM_cs, // 1 = shell owns the bus
    inout [15:0] bus_RAM_data,

);

.....

  wire [15:0] w_ROM_data;
  wire [15:0] w_ROM_addr;
  always @* begin
    if (bus_ROM_cs) begin
      w_ROM_addr = bus_ROM_addr;
      w_ROM_data = bus_ROM_data;
    end
    else begin
      w_ROM_addr = w_CPU_ROM_addr;
      w_ROM_data = ROM[w_ROM_addr];
    end
  end

 ....

yosys complains

Warning: wire 'w_ROM_addr' is assigned in a block at system.v:38.7-38.32.
Warning: wire 'w_ROM_data' is assigned in a block at system.v:39.7-39.32.
Warning: wire 'w_ROM_addr' is assigned in a block at system.v:42.7-42.34.
Warning: wire 'w_ROM_data' is assigned in a block at system.v:43.7-43.35.

I know I am not supposed to assign wires in clocked always blocks. But I thought assigning wires was the point of ‘always @*’ blocks.

I have learned which yosys warnings can be safely ignored, but this one I am not sure about