I’ve been writing a simple VGA 640×480 controller in VHDL for my Cylcone IV development board. It has 50 MHz clock.

I’ve rewritten the code several times (even in Verilog), but it doesn’t work (my monitor can’t catch the signal). However, example for my board from the manufacturer works, so I know that all the components on board are functional.

Can you review my code and check if there are any errors? Because I’m completely lost.

vga2.vhd (main file):

library ieee;
use ieee.std_logic_1164.all;

entity vga2 is
    port (
        i_clock : in  std_logic;
        i_reset : in  std_logic;
        
        o_horizontal_sync : out std_logic;
        o_vertical_sync : out std_logic;
        o_color: out std_logic_vector (2 downto 0)
    );
end vga2;

architecture struct of vga2 is
    component vga
        port (
            i_clock : in  std_logic;
            i_reset : in  std_logic;
            
            i_color : in std_logic_vector (2 downto 0);
            
            o_horizontal_sync : out std_logic;
            o_vertical_sync : out std_logic;
            o_color: out std_logic_vector (2 downto 0);
            
            o_x : out std_logic_vector (9 downto 0);
            o_y : out std_logic_vector (9 downto 0);
            o_data_allow : out std_logic
        );
    end component;
    
    constant COLOR : std_logic_vector (2 downto 0) := "101";
begin
    c_vga: vga
        port map (
            i_clock => i_clock,
            i_reset => i_reset,
            
            i_color => COLOR,
            
            o_horizontal_sync => o_horizontal_sync,
            o_vertical_sync => o_vertical_sync,
            o_color => o_color
        );
end struct;

vga.vhd:

library ieee;
use ieee.std_logic_1164.all;

entity vga is
    port (
        i_clock : in  std_logic;
        i_reset : in  std_logic;
        
        i_color : in std_logic_vector (2 downto 0);
        
        o_horizontal_sync : out std_logic;
        o_vertical_sync : out std_logic;
        o_color: out std_logic_vector (2 downto 0);
        
        o_x : out std_logic_vector (9 downto 0);
        o_y : out std_logic_vector (9 downto 0);
        o_data_allow : out std_logic
    );
end vga;

architecture struct of vga is
    component clock_half
        port (
            i_clock : in  std_logic;
            i_reset : in  std_logic;
            o_clock : out std_logic
        );
    end component;
    
    component vga_480p
        port (
            i_clock : in  std_logic;
            i_reset : in  std_logic;
            
            o_horizontal_sync : out std_logic;
            o_vertical_sync : out std_logic;
            
            o_x : out std_logic_vector (9 downto 0);
            o_y : out std_logic_vector (9 downto 0);
            o_data_allow : out std_logic
        );
    end component;

    signal s_pixel_clock : std_logic;
    signal s_data_allow : std_logic;
    
    constant BLACK : std_logic_vector (2 downto 0) := "000";
begin
    c_clock_half : clock_half
        port map (
            i_clock => i_clock,
            i_reset => i_reset,
            
            o_clock => s_pixel_clock
        );
        
    c_vga_480p : vga_480p
        port map (
            i_clock => s_pixel_clock,
            i_reset => i_reset,
            
            o_horizontal_sync => o_horizontal_sync,
            o_vertical_sync => o_vertical_sync,
            
            o_x => o_x,
            o_y => o_y,
            o_data_allow => s_data_allow
        );
    
    o_color <= i_color when s_data_allow = '1' else BLACK;
    
    o_data_allow <= s_data_allow;
end struct;

clock_half.vhd:

library ieee;
use ieee.std_logic_1164.all;

entity clock_half is
    port (
        i_clock : in  std_logic;
        i_reset : in  std_logic;
        o_clock : out std_logic
    );
end clock_half;

architecture rtl of clock_half is
    signal r_clock : std_logic;
begin
    process (i_clock) is
    begin
        if rising_edge(i_clock) then
            if i_reset = '1' then
                r_clock <= '0';
            else
                r_clock <= not r_clock;
            end if;
        end if;
    end process;
    
    o_clock <= r_clock;
end rtl;

vga_480.vhd:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity vga_480p is
    port (
        i_clock : in  std_logic;
        i_reset : in  std_logic;
            
        o_horizontal_sync : out std_logic;
        o_vertical_sync : out std_logic;
        
        o_x : out std_logic_vector (9 downto 0);
        o_y : out std_logic_vector (9 downto 0);
        o_data_allow : out std_logic
    );
end vga_480p;

architecture behavioral of vga_480p is
    constant HORIZONTAL_ACTIVE_COUNT : natural := 640;
    constant HORIZONTAL_FRONT_PORCH  : natural := 16;
   constant HORIZONTAL_SYNC_WIDTH   : natural := 96;
   constant HORIZONTAL_BACK_PORCH   : natural := 48;

   constant VERTICAL_ACTIVE_COUNT   : natural := 480;
   constant VERTICAL_FRONT_PORCH    : natural := 10;
   constant VERTICAL_SYNC_WIDTH     : natural := 2;
   constant VERTICAL_BACK_PORCH     : natural := 33;
          
    constant HORIZONTAL_ACTIVE_END : natural := HORIZONTAL_ACTIVE_COUNT - 1;
   constant HORIZONTAL_SYNC_START : natural := HORIZONTAL_ACTIVE_END   + HORIZONTAL_FRONT_PORCH;
   constant HORIZONTAL_SYNC_END   : natural := HORIZONTAL_SYNC_START   + HORIZONTAL_SYNC_WIDTH;
   constant HORIZONTAL_LAST       : natural := HORIZONTAL_SYNC_END     + HORIZONTAL_BACK_PORCH;
    
   constant VERTICAL_ACTIVE_END   : natural := VERTICAL_ACTIVE_COUNT   - 1;
   constant VERTICAL_SYNC_START   : natural := VERTICAL_ACTIVE_END     + VERTICAL_FRONT_PORCH;
   constant VERTICAL_SYNC_END     : natural := VERTICAL_SYNC_START     + VERTICAL_SYNC_WIDTH;
   constant VERTICAL_LAST         : natural := VERTICAL_SYNC_END      + VERTICAL_BACK_PORCH;
    
    signal s_x : integer := 0;
    signal s_y : integer := 0;
begin
    o_x <= std_logic_vector(to_unsigned(s_x, o_x'length));
    o_y <= std_logic_vector(to_unsigned(s_y, o_y'length));
    
    o_data_allow <= '1' when (s_x < HORIZONTAL_ACTIVE_END) and (s_y < VERTICAL_ACTIVE_END) else '0';
    
    o_horizontal_sync <= '0' when (s_x >= HORIZONTAL_SYNC_START) and (s_x < HORIZONTAL_SYNC_END) else '1';
    o_vertical_sync <= '0' when (s_y >= VERTICAL_SYNC_START) and (s_y < VERTICAL_SYNC_END) else '1';
    
    process (i_clock)
    begin
        if rising_edge(i_clock) then
            if i_reset = '1' then
                s_x <= 0;
                s_y <= 0;
            end if;
            
            if s_x = HORIZONTAL_LAST then
                s_x <= 0;
                if s_y = VERTICAL_LAST then 
                    s_y <= 0;
                else
                    s_y <= s_y + 1;
                end if;
            else
                s_x <= s_x + 1;
            end if;
        end if;
    end process;
end behavioral;