I am running into an error on Vivado. I am trying to run implementation to program my Basys board, but I am running into the following error:
[DRC MDRV-1] Multiple Driver Nets: Net ScrlFSM/RLC2B/DER1/DFF_R1/DFF1/nextS[1] has multiple drivers: ScrlFSM/RLC2B/DER1/DFF_R1/DFF1/Q_i_3/O, and ScrlFSM/RLC2B/DER1/DFF_R1/DFF1/Q_i_2/O.
This is my VHDL for my top level:
architecture Structural of xxxxxxxxxxx is
component WordTo4DigitDisplayDriver is
port (
WORD : in STD_LOGIC_VECTOR(15 downto 0);
PULSE : in STD_LOGIC;
CLK : in STD_LOGIC;
SEGMENT : out STD_LOGIC_VECTOR(0 to 6);
ANODE : out STD_LOGIC_VECTOR(3 downto 0)
);
end component;
component PulseGenerator_1ms is
port (
CLK : in STD_LOGIC;
PULSE : out STD_LOGIC
);
end component;
signal pulse_1ms : STD_LOGIC;
component ScrollFSM is
port (
L : in STD_LOGIC;
R : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
DISPLAY : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
begin
Wt4DDD: WordTo4DigitDisplayDriver
port map (
WORD => SWITCH(15 downto 0),
PULSE => pulse_1ms,
CLK => CLK,
SEGMENT => SEGMENT,
ANODE => ANODE
);
PulseGen: PulseGenerator_1ms
port map (
CLK => CLK,
PULSE => pulse_1ms
);
ScrlFSM: ScrollFSM
port map (
L => BTNL,
R => BTNR,
CLK => CLK,
RESET => BTND,
DISPLAY (1 downto 0) => LED(15 downto 14)
);
end architecture;
I read through possible causes of this, and it seems like I am tying multiple outputs together. I cannot find any case of that in my top level, so I’m not sure what the issue is. I tried resolving any possible errors in both my top level and in the rest of my VHDL but am still getting the same error.
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