I am trying to write a data path in VHDL and I’m struggling with the part of the immediate instructions where I have to take the 16 bit immediate part of the instruction and convert it to a 32 bit and also shift it left by 2 or 16 depending on the Opcode of the instruction. I decided to do this with a FSM. this is the code i have written so far:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Immed_conversion_unit is
    Port ( Instruction : in  STD_LOGIC_VECTOR (31 downto 0);
           Immediate_out : out  STD_LOGIC_VECTOR (31 downto 0));
end Immed_conversion_unit;

architecture Behavioral of Immed_conversion_unit is

signal immed: STD_LOGIC_VECTOR(31 downto 0):="00000000000000000000000000000000";
signal result: STD_LOGIC_VECTOR(31 downto 0):="00000000000000000000000000000000";

begin 
process (Instruction)
begin
    case Instruction(31 downto 26) is
        when "110010" | "110011" => result<=std_logic_vector(resize(unsigned(Instruction(15 downto 0)), 32));
        when "000011" | "000111" | "001111" | "011111" | "110000" | "111000" =>  result<=std_logic_vector(resize(signed(Instruction(15 downto 0)), 32));
        when "111111" | "010000" | "010001" =>
                result<=std_logic_vector(resize(signed(Instruction(15 downto 0)), 32));
                result<=std_logic_vector(shift_left(unsigned(result), 2));
        when "111001" =>
                result<=std_logic_vector(resize(signed(Instruction(15 downto 0)), 32));
                result<=std_logic_vector(shift_left(unsigned(result), 16));
        when others => result<= "00000000000000000000000000000000";
    end case;
end process;
    
    Immediate_out<=result;
end Behavioral;  

The problem is that when it has to resize and also shift left it outputs all zeros.

I think that problem is in the shift_left function. Probably I am using it wrong. Any suggestions on how to fix my VHDL code or more generally how to to tackle this task are welcome. Thanks in advance