I’m seeing failing errors both from iverilog and verilator in a module which has a wire instantiated based on a condition. This was originally happening in a SystemVerilog module I got from someone else who had apparently successfully simulated and synthesized the code with Xilinx tools. I’ve created a much simpler verilog example that exhibits the same problem.

The code:

module test_gen
    #(parameter OPERATION_TYPE = 0)
    (
        input  logic [31:0] a,
        input  logic [31:0] b,
        output logic [63:0] z
    );
    generate 
        if (OPERATION_TYPE == 0) begin
        wire foo;
        end
    endgenerate
    wire [63:0] zz;

    generate
        always @ (a,b) begin
        if (OPERATION_TYPE == 0) begin
            assign foo = a[0] & b[0];
            z <= {foo, 63'b0};
        end
        else if (OPERATION_TYPE == 1) begin
            z <= a - b;
        end
        else if (OPERATION_TYPE == 2) begin
            z <= (a << 1) + b; // 2a+b
        end
        else begin
            z <= b - a;
        end
        end
    endgenerate
endmodule

iverilog fails with the message:

test_gen.v:18: error: Could not find
variable foo'' in test_gen” test_gen.v:19: error: Unable to bind
wire/reg/memory foo' in test_gen’
(it will compile if OPERATION_TYPE is set to a non-zero value)

verilator 4.211 issues an error as well:

%Error: test_gen.v:18:20: Can’t find definition of variable: ‘foo’
18 | assign foo = a[0] & b[0];
| ^~~ %Error: Exiting due to 1 error(s)

So it’s as if the wire foo was never instantiated even though the condition was true.

Is conditionally instantiating a wire like this legal Verilog/SystemVerilog? Or is it not legal and the Xilinx tools are just more lenient?