I am trying to write a code for RAM and ROM modules and put them all together under a joint module but my systemOutput in my top module is not working as expected, it should have the same value as dataOut but it only has the value dataOut was initiated with. But isn’t systemOutput just an output wire from the dataOut register?

module ROM (
input [2:0] addr, // Address input
output reg [7:0] dataOut // Data output
);

  reg [7:0] rom [0:7] ;
  
  
  
    initial begin
        rom[0] = 8'b00000000;  // Address 0
        rom[1] = 8'b00000001;  // Address 1
        rom[2] = 8'b00000010;  // Address 2
        rom[3] = 8'b00100011;  // Address 3
        rom[4] = 8'b11000100;  // Address 4
        rom[5] = 8'b01100101;  // Address 5
        rom[6] = 8'b00011110;  // Address 6
        rom[7] = 8'b01000101;  // Address 7
    end

 
  always @(addr) begin
        
        
        dataOut<=rom[addr]; 
      
end
endmodule


module Bitwise_Manipulation_RAM (
input mode, // 0 for write, 1 for read
input [2:0] addr, // RAM address
input [1:0] operation, // Operation code
input [7:0] dataIn, // Input data
input [7:0] romData, // Data from ROM used in operations
input CLK, // Clock signal
output reg [7:0] dataOut // Output data
);

  reg [7:0] memory [0:7];
  
  initial begin
            
        memory[0] = 8'b00000000;  // Address 0
        memory[1] = 8'b00000000;  // Address 1
        memory[2] = 8'b00000000;  // Address 2
        memory[3] = 8'b00000000;  // Address 3
        memory[4] = 8'b00000000;  // Address 4
        memory[5] = 8'b00000000;  // Address 5
        memory[6] = 8'b00000000;  // Address 6
        memory[7] = 8'b00000000;  // Address 7
          dataOut=8'b01010010; //systemOutput has this value and it does not change 
    end


 

always @ (posedge CLK or posedge mode ) begin 
if (mode==1'b1) begin
    dataOut<=memory[addr];
    
    end 

else if (mode==1'b0 ) begin 

    if (operation==2'b00) begin
        dataOut <= (romData & dataIn);
        $display("data out is %b",dataOut);
        memory[addr]<=(romData & dataIn);
    
    end
    
    else if (operation==2'b01) begin
     dataOut <= (romData | dataIn);
        memory[addr]<=(romData | dataIn);
        $display("data out is %b",dataOut);
    end


    else if (operation==2'b10) begin
    dataOut <= (romData ^ dataIn);
    memory[addr]<=(romData ^ dataIn);
    $display("data out is %b",dataOut);
    end
    
    else if (operation==2'b11) begin
    dataOut <= ~(romData & dataIn);
    memory[addr]<=~(romData & dataIn);
    $display("data out is %b",dataOut);
    end
end




end 



endmodule

module Combined_Memory_System (
input mode,
input [2:0] systemAddr,
input [7:0] dataIn,
input [1:0] operation,
input CLK,
output [7:0] systemOutput
);
wire [7:0] romData; // Data read from ROM

ROM rom(
.addr(systemAddr),
.dataOut(romData)
);


Bitwise_Manipulation_RAM ram(
.mode(mode),
.addr(systemAddr),
.operation(operation),
.dataIn(dataIn),
.romData(romData),
.CLK(CLK),
.dataOut(systemOutput)
);
 



endmodule

maybe dataOut is being assigned with different values at the same time??