module Booth_alg(
output [15:0]result,
output reg [15:0]temp,
output reg [2:0]count,c1,cnt,
input clk,rst,
input [7:0]M,Q);
reg [15:0]mult;
reg [7:0]m;
always@(*) m=(~M)+1'b1;
always@(posedge clk) begin
if(rst) begin
count<=3'd7;
cnt<=0;
c1<=3'd0;
{temp,mult}<=32'd0;
end
else begin
count<=count-1;
if((Q[count] ^ Q[count-1]) == 1'b1) begin
cnt<=count;
c1<=c1+1;
if((c1%2)==1) temp<={8'b00000000,M};
else temp<={{8{m[7]}},m};
temp<=temp<<cnt;
mult<=mult+temp;
end
else begin
cnt<=cnt;
c1<=c1;
temp<=0;
mult<=mult;
end
end
end
assign result=mult;
endmodule
module tb;
wire [15:0]result,temp;
wire [2:0]count,c1,cnt;
reg [7:0]M,Q;
reg clk,rst;
Booth_alg DUT(result,temp,count,c1,cnt,clk,rst,M,Q);
always #5 clk=~clk;
initial begin
$monitor("t=%g clk=%b rst=%b M=%b Q=%b count=%d cnt=%d c1=%d temp=%b result=%b",$time,clk,rst,M,Q,count,cnt,c1,temp,result);
$dumpfile("tb.vcd");
$dumpvars(0,tb);
{clk,rst}=0;
#5 rst=1'b1;
#5 rst=1'b0;
#5 M=8'b00001011; Q=8'b00001110;
#300 $finish;
end
endmodule
I got the output as shown below:
t=0 clk=0 rst=0 M=xxxxxxxx Q=xxxxxxxx count=x cnt=x c1=x temp=xxxxxxxxxxxxxxxx result=xxxxxxxxxxxxxxxx
t=5 clk=1 rst=1 M=xxxxxxxx Q=xxxxxxxx count=7 cnt=0 c1=0 temp=0000000000000000 result=0000000000000000
t=10 clk=0 rst=0 M=xxxxxxxx Q=xxxxxxxx count=7 cnt=0 c1=0 temp=0000000000000000 result=0000000000000000
t=15 clk=1 rst=0 M=00001011 Q=00001110 count=6 cnt=0 c1=0 temp=0000000000000000 result=0000000000000000
t=20 clk=0 rst=0 M=00001011 Q=00001110 count=6 cnt=0 c1=0 temp=0000000000000000 result=0000000000000000
t=25 clk=1 rst=0 M=00001011 Q=00001110 count=5 cnt=0 c1=0 temp=0000000000000000 result=0000000000000000
t=30 clk=0 rst=0 M=00001011 Q=00001110 count=5 cnt=0 c1=0 temp=0000000000000000 result=0000000000000000
t=35 clk=1 rst=0 M=00001011 Q=00001110 count=4 cnt=0 c1=0 temp=0000000000000000 result=0000000000000000
t=40 clk=0 rst=0 M=00001011 Q=00001110 count=4 cnt=0 c1=0 temp=0000000000000000 result=0000000000000000
t=45 clk=1 rst=0 M=00001011 Q=00001110 count=3 cnt=4 c1=1 temp=0000000000000000 result=0000000000000000
t=50 clk=0 rst=0 M=00001011 Q=00001110 count=3 cnt=4 c1=1 temp=0000000000000000 result=0000000000000000
t=55 clk=1 rst=0 M=00001011 Q=00001110 count=2 cnt=4 c1=1 temp=0000000000000000 result=0000000000000000
t=60 clk=0 rst=0 M=00001011 Q=00001110 count=2 cnt=4 c1=1 temp=0000000000000000 result=0000000000000000
t=65 clk=1 rst=0 M=00001011 Q=00001110 count=1 cnt=4 c1=1 temp=0000000000000000 result=0000000000000000
t=70 clk=0 rst=0 M=00001011 Q=00001110 count=1 cnt=4 c1=1 temp=0000000000000000 result=0000000000000000
t=75 clk=1 rst=0 M=00001011 Q=00001110 count=0 cnt=1 c1=2 temp=0000000000000000 result=0000000000000000
t=80 clk=0 rst=0 M=00001011 Q=00001110 count=0 cnt=1 c1=2 temp=0000000000000000 result=0000000000000000
t=85 clk=1 rst=0 M=00001011 Q=00001110 count=7 cnt=1 c1=2 temp=0000000000000000 result=0000000000000000
t=90 clk=0 rst=0 M=00001011 Q=00001110 count=7 cnt=1 c1=2 temp=0000000000000000 result=0000000000000000
t=95 clk=1 rst=0 M=00001011 Q=00001110 count=6 cnt=1 c1=2 temp=0000000000000000 result=0000000000000000
t=100 clk=0 rst=0 M=00001011 Q=00001110 count=6 cnt=1 c1=2 temp=0000000000000000 result=0000000000000000
t=105 clk=1 rst=0 M=00001011 Q=00001110 count=5 cnt=1 c1=2 temp=0000000000000000 result=0000000000000000
t=110 clk=0 rst=0 M=00001011 Q=00001110 count=5 cnt=1 c1=2 temp=0000000000000000 result=0000000000000000
t=115 clk=1 rst=0 M=00001011 Q=00001110 count=4 cnt=1 c1=2 temp=0000000000000000 result=0000000000000000
t=120 clk=0 rst=0 M=00001011 Q=00001110 count=4 cnt=1 c1=2 temp=0000000000000000 result=0000000000000000
t=125 clk=1 rst=0 M=00001011 Q=00001110 count=3 cnt=4 c1=3 temp=0000000000000000 result=0000000000000000
t=130 clk=0 rst=0 M=00001011 Q=00001110 count=3 cnt=4 c1=3 temp=0000000000000000 result=0000000000000000
t=135 clk=1 rst=0 M=00001011 Q=00001110 count=2 cnt=4 c1=3 temp=0000000000000000 result=0000000000000000
t=140 clk=0 rst=0 M=00001011 Q=00001110 count=2 cnt=4 c1=3 temp=0000000000000000 result=0000000000000000
t=145 clk=1 rst=0 M=00001011 Q=00001110 count=1 cnt=4 c1=3 temp=0000000000000000 result=0000000000000000
t=150 clk=0 rst=0 M=00001011 Q=00001110 count=1 cnt=4 c1=3 temp=0000000000000000 result=0000000000000000
t=155 clk=1 rst=0 M=00001011 Q=00001110 count=0 cnt=1 c1=4 temp=0000000000000000 result=0000000000000000
t=160 clk=0 rst=0 M=00001011 Q=00001110 count=0 cnt=1 c1=4 temp=0000000000000000 result=0000000000000000
t=165 clk=1 rst=0 M=00001011 Q=00001110 count=7 cnt=1 c1=4 temp=0000000000000000 result=0000000000000000
t=170 clk=0 rst=0 M=00001011 Q=00001110 count=7 cnt=1 c1=4 temp=0000000000000000 result=0000000000000000
t=175 clk=1 rst=0 M=00001011 Q=00001110 count=6 cnt=1 c1=4 temp=0000000000000000 result=0000000000000000
t=180 clk=0 rst=0 M=00001011 Q=00001110 count=6 cnt=1 c1=4 temp=0000000000000000 result=0000000000000000
t=185 clk=1 rst=0 M=00001011 Q=00001110 count=5 cnt=1 c1=4 temp=0000000000000000 result=0000000000000000
t=190 clk=0 rst=0 M=00001011 Q=00001110 count=5 cnt=1 c1=4 temp=0000000000000000 result=0000000000000000
t=195 clk=1 rst=0 M=00001011 Q=00001110 count=4 cnt=1 c1=4 temp=0000000000000000 result=0000000000000000
t=200 clk=0 rst=0 M=00001011 Q=00001110 count=4 cnt=1 c1=4 temp=0000000000000000 result=0000000000000000
t=205 clk=1 rst=0 M=00001011 Q=00001110 count=3 cnt=4 c1=5 temp=0000000000000000 result=0000000000000000
t=210 clk=0 rst=0 M=00001011 Q=00001110 count=3 cnt=4 c1=5 temp=0000000000000000 result=0000000000000000
t=215 clk=1 rst=0 M=00001011 Q=00001110 count=2 cnt=4 c1=5 temp=0000000000000000 result=0000000000000000
t=220 clk=0 rst=0 M=00001011 Q=00001110 count=2 cnt=4 c1=5 temp=0000000000000000 result=0000000000000000
t=225 clk=1 rst=0 M=00001011 Q=00001110 count=1 cnt=4 c1=5 temp=0000000000000000 result=0000000000000000
t=230 clk=0 rst=0 M=00001011 Q=00001110 count=1 cnt=4 c1=5 temp=0000000000000000 result=0000000000000000
t=235 clk=1 rst=0 M=00001011 Q=00001110 count=0 cnt=1 c1=6 temp=0000000000000000 result=0000000000000000
t=240 clk=0 rst=0 M=00001011 Q=00001110 count=0 cnt=1 c1=6 temp=0000000000000000 result=0000000000000000
t=245 clk=1 rst=0 M=00001011 Q=00001110 count=7 cnt=1 c1=6 temp=0000000000000000 result=0000000000000000
t=250 clk=0 rst=0 M=00001011 Q=00001110 count=7 cnt=1 c1=6 temp=0000000000000000 result=0000000000000000
t=255 clk=1 rst=0 M=00001011 Q=00001110 count=6 cnt=1 c1=6 temp=0000000000000000 result=0000000000000000
t=260 clk=0 rst=0 M=00001011 Q=00001110 count=6 cnt=1 c1=6 temp=0000000000000000 result=0000000000000000
t=265 clk=1 rst=0 M=00001011 Q=00001110 count=5 cnt=1 c1=6 temp=0000000000000000 result=0000000000000000
t=270 clk=0 rst=0 M=00001011 Q=00001110 count=5 cnt=1 c1=6 temp=0000000000000000 result=0000000000000000
t=275 clk=1 rst=0 M=00001011 Q=00001110 count=4 cnt=1 c1=6 temp=0000000000000000 result=0000000000000000
t=280 clk=0 rst=0 M=00001011 Q=00001110 count=4 cnt=1 c1=6 temp=0000000000000000 result=0000000000000000
t=285 clk=1 rst=0 M=00001011 Q=00001110 count=3 cnt=4 c1=7 temp=0000000000000000 result=0000000000000000
t=290 clk=0 rst=0 M=00001011 Q=00001110 count=3 cnt=4 c1=7 temp=0000000000000000 result=0000000000000000
t=295 clk=1 rst=0 M=00001011 Q=00001110 count=2 cnt=4 c1=7 temp=0000000000000000 result=0000000000000000
t=300 clk=0 rst=0 M=00001011 Q=00001110 count=2 cnt=4 c1=7 temp=0000000000000000 result=0000000000000000
t=305 clk=1 rst=0 M=00001011 Q=00001110 count=1 cnt=4 c1=7 temp=0000000000000000 result=0000000000000000
t=310 clk=0 rst=0 M=00001011 Q=00001110 count=1 cnt=4 c1=7 temp=0000000000000000 result=0000000000000000
bm.v:60: $finish called at 315 (1s)
t=315 clk=1 rst=0 M=00001011 Q=00001110 count=0 cnt=1 c1=0 temp=0000000000000000 result=0000000000000000
I was excepting the result to be the multiplication of M and Q.
You are using a poor coding style when assigning to temp. You use multiple nonblocking assignments to the same variable:
if((c1%2)==1) temp<={8'b00000000,M};
else temp<={{8{m[7]}},m};
temp<=temp<<cnt;
The 1st assignment is in the if/else, and the 2nd assignment is in the 3rd line shown. This is a confusing way to write Verilog because it produces unexpected results like this. Some synthesis linting tools would report a violation for this code.
You need to rework your code. There is no reason to try to place all of that code into the same always block. It is often clearer to create multiple always blocks.