I have 2 STM32F407 processors talking via SPI. The slave monitors many inputs, when something of interest happens it interrupts the master which starts the SPI transfer. This process is register based (NO HAL) and 100% driven by interrupts and DMA and everything works as it should. The problem is when SPI CRC is added. The Reference Manual RM0090 Rev 19 pages 891 and 892 provide CRC configuration details. It indicates (I think) that the NSS line needs to be held low at least into the beginning of the CRC transmission. See steps 5 and 6 page 892.

If I leave the NSS line low after the DMA transfer of the data, the CRC is received and tested without any errors. All is good. If I bring the NSS line high at the end of DMA transfer I receive 0x00 for the CRC and as expected get a CRC error.

My issue is that if I leave the NSS line low to do the CRC transfer, I do not have anything to signal me when that CRC transfer is complete so that the NSS line can be raised again. I have spent several days trying to solve this but have not found any way to detect the end of CRC transfer when using DMA.

I must be missing something. Others must have this configuration working. If anyone can give me clue as to what signal triggers the end of an SPI transfer with CRC using DMA and possibly how it should be configured, I would be most grateful.

Thanks in advance for any help.
Jim

NSS going high at end of 4 bytes of data.

NSS staying low at end of 4 bytes of data.