I am working on a PCIe DMA design. I am using DMA/Bridge Subsystem for PCI Express 4.1 with AXI interconnect 2.1 (connections are given below) on Vivado 2023.2. I am using AXI-Lite as interface. I have a script in python that writes to PCIe using pypcie library (script is provided below). Script is run with python 3.6.9 on Ubuntu 18.04. I am using Zynq7030 FPGA on enclustra ZX5 modeule with PE1 base board.

When i run the script, i see two read requests are present on master AXI-Lite port of xdma for a single 32-bit read request (ILA screenshot provided below, read request is sent to address 50000 two times and returns same doubleword twice)

I have run the simulations in example design and observed that this is not the normal behavior for Xilinx IP.

I have also reached to xdma registers with dd command from system terminal and dd command produces a single read request. Using the command;

sudo dd if=/dev/mem bs=1 count=1 skip=$((0xa2100000 / 1)) status=none | hexdump -e ‘1/4 “%08xn”‘

So, i am assuming this double read behavior comes from PyPCIe library in python.

I want to reach xdma registers using python, but be able to reach the xdma registers in a single read request command. Is there a way i can achieve this in python?

python script :

from pypcie import Device
import time

d = Device(“0000:01:00.0”)

bar = d.bar[0]

try:
while True:

    print("Running...")


    bar.write(0x50000, 0xdeadbeef)
    bar.write(0x50004, 0xbeef)
    bar.write(0x50008, 0xface)

    ret = bar.read(0x50000)
    print(hex(ret))
    ret = bar.read(0x50004)
    print(hex(ret))
    ret = bar.read(0x50008)
    print(hex(ret))

except KeyboardInterrupt:
print(“nKeyboard interrupt received. Exiting loop.”)

ILA Screenshot
enter image description here

AXI connections
enter image description here

I have tried to run the script that i provided and got double read requests, i have used the dd command that i provided and got single request. i want to be able to get single read request using python