I wrote a code to display ultrasonic HC-SR04 sensor. However, I can’t get data from it, hence seven segment does not display any number. I guess it is related with my constraint. Can you check it?
First topmodule, then constraint code added.
<code>-------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
entity topmoduleultrasonic is
Port ( pin_trigger : out STD_LOGIC;
pin_pulse : in STD_LOGIC;
clock : in STD_LOGIC;
displayA : out STD_LOGIC;
displayB : out STD_LOGIC;
displayC : out STD_LOGIC;
displayD : out STD_LOGIC;
tsegA : out STD_LOGIC;
tsegB : out STD_LOGIC;
tsegC : out STD_LOGIC;
tsegD : out STD_LOGIC;
tsegE : out STD_LOGIC;
tsegF : out STD_LOGIC;
tsegG : out STD_LOGIC);
end topmoduleultrasonic;
architecture Behavioral of topmoduleultrasonic is
component obstacle_detection_sensor is
Port ( fpgaclock : in STD_LOGIC;
pulse : in STD_LOGIC;
out_trigger : out STD_LOGIC;
obstacle_in_m : out STD_LOGIC_VECTOR (3 downto 0);
obstacle_in_dm : out STD_LOGIC_VECTOR (3 downto 0);
obstacle_in_cm : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component seg_driver is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
C : in STD_LOGIC_VECTOR (3 downto 0);
D : in STD_LOGIC_VECTOR (3 downto 0);
sevensegmentA : out STD_LOGIC;
sevensegmentB : out STD_LOGIC;
sevensegmentC : out STD_LOGIC;
sevensegmentD : out STD_LOGIC;
sevensegmentE : out STD_LOGIC;
sevensegmentF : out STD_LOGIC;
sevensegmentG : out STD_LOGIC;
select_A : out STD_LOGIC;
select_B : out STD_LOGIC;
select_C : out STD_LOGIC;
select_D : out STD_LOGIC;
clock : in STD_LOGIC);
end component;
--4 bit internal signal
signal signalA : std_logic_vector(3 downto 0);
signal signalB : std_logic_vector(3 downto 0);
signal signalC : std_logic_vector(3 downto 0);
signal signalD : std_logic_vector(3 downto 0);
--sensor data signals
signal s_m : std_logic_vector(3 downto 0);
signal s_dm : std_logic_vector(3 downto 0);
signal s_cm : std_logic_vector(3 downto 0);
begin
--assigning components to output
uut3: seg_driver port map (
A => signalA,
B => signalB,
C => signalC,
D => signalD,
sevensegmentA => tsegA,
sevensegmentB => tsegB,
sevensegmentC => tsegC,
sevensegmentD => tsegD,
sevensegmentE => tsegE,
sevensegmentF => tsegF,
sevensegmentG => tsegG,
select_A => displayA,
select_B => displayB,
select_C => displayC,
select_D => displayD,
clock => clock);
uut4 : obstacle_detection_sensor PORT MAP(
fpgaclock => clock,
out_trigger => pin_trigger,
pulse => pin_pulse,
obstacle_in_m => s_m,
obstacle_in_dm => s_dm,
obstacle_in_cm => s_cm );
signalA <= s_cm;
signalB <= s_dm;
signalC <= s_m;
signalD <= "0000";
end Behavioral;
</code>
<code>-------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
entity topmoduleultrasonic is
Port ( pin_trigger : out STD_LOGIC;
pin_pulse : in STD_LOGIC;
clock : in STD_LOGIC;
displayA : out STD_LOGIC;
displayB : out STD_LOGIC;
displayC : out STD_LOGIC;
displayD : out STD_LOGIC;
tsegA : out STD_LOGIC;
tsegB : out STD_LOGIC;
tsegC : out STD_LOGIC;
tsegD : out STD_LOGIC;
tsegE : out STD_LOGIC;
tsegF : out STD_LOGIC;
tsegG : out STD_LOGIC);
end topmoduleultrasonic;
architecture Behavioral of topmoduleultrasonic is
component obstacle_detection_sensor is
Port ( fpgaclock : in STD_LOGIC;
pulse : in STD_LOGIC;
out_trigger : out STD_LOGIC;
obstacle_in_m : out STD_LOGIC_VECTOR (3 downto 0);
obstacle_in_dm : out STD_LOGIC_VECTOR (3 downto 0);
obstacle_in_cm : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component seg_driver is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
C : in STD_LOGIC_VECTOR (3 downto 0);
D : in STD_LOGIC_VECTOR (3 downto 0);
sevensegmentA : out STD_LOGIC;
sevensegmentB : out STD_LOGIC;
sevensegmentC : out STD_LOGIC;
sevensegmentD : out STD_LOGIC;
sevensegmentE : out STD_LOGIC;
sevensegmentF : out STD_LOGIC;
sevensegmentG : out STD_LOGIC;
select_A : out STD_LOGIC;
select_B : out STD_LOGIC;
select_C : out STD_LOGIC;
select_D : out STD_LOGIC;
clock : in STD_LOGIC);
end component;
--4 bit internal signal
signal signalA : std_logic_vector(3 downto 0);
signal signalB : std_logic_vector(3 downto 0);
signal signalC : std_logic_vector(3 downto 0);
signal signalD : std_logic_vector(3 downto 0);
--sensor data signals
signal s_m : std_logic_vector(3 downto 0);
signal s_dm : std_logic_vector(3 downto 0);
signal s_cm : std_logic_vector(3 downto 0);
begin
--assigning components to output
uut3: seg_driver port map (
A => signalA,
B => signalB,
C => signalC,
D => signalD,
sevensegmentA => tsegA,
sevensegmentB => tsegB,
sevensegmentC => tsegC,
sevensegmentD => tsegD,
sevensegmentE => tsegE,
sevensegmentF => tsegF,
sevensegmentG => tsegG,
select_A => displayA,
select_B => displayB,
select_C => displayC,
select_D => displayD,
clock => clock);
uut4 : obstacle_detection_sensor PORT MAP(
fpgaclock => clock,
out_trigger => pin_trigger,
pulse => pin_pulse,
obstacle_in_m => s_m,
obstacle_in_dm => s_dm,
obstacle_in_cm => s_cm );
signalA <= s_cm;
signalB <= s_dm;
signalC <= s_m;
signalD <= "0000";
end Behavioral;
</code>
-------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
entity topmoduleultrasonic is
Port ( pin_trigger : out STD_LOGIC;
pin_pulse : in STD_LOGIC;
clock : in STD_LOGIC;
displayA : out STD_LOGIC;
displayB : out STD_LOGIC;
displayC : out STD_LOGIC;
displayD : out STD_LOGIC;
tsegA : out STD_LOGIC;
tsegB : out STD_LOGIC;
tsegC : out STD_LOGIC;
tsegD : out STD_LOGIC;
tsegE : out STD_LOGIC;
tsegF : out STD_LOGIC;
tsegG : out STD_LOGIC);
end topmoduleultrasonic;
architecture Behavioral of topmoduleultrasonic is
component obstacle_detection_sensor is
Port ( fpgaclock : in STD_LOGIC;
pulse : in STD_LOGIC;
out_trigger : out STD_LOGIC;
obstacle_in_m : out STD_LOGIC_VECTOR (3 downto 0);
obstacle_in_dm : out STD_LOGIC_VECTOR (3 downto 0);
obstacle_in_cm : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component seg_driver is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
C : in STD_LOGIC_VECTOR (3 downto 0);
D : in STD_LOGIC_VECTOR (3 downto 0);
sevensegmentA : out STD_LOGIC;
sevensegmentB : out STD_LOGIC;
sevensegmentC : out STD_LOGIC;
sevensegmentD : out STD_LOGIC;
sevensegmentE : out STD_LOGIC;
sevensegmentF : out STD_LOGIC;
sevensegmentG : out STD_LOGIC;
select_A : out STD_LOGIC;
select_B : out STD_LOGIC;
select_C : out STD_LOGIC;
select_D : out STD_LOGIC;
clock : in STD_LOGIC);
end component;
--4 bit internal signal
signal signalA : std_logic_vector(3 downto 0);
signal signalB : std_logic_vector(3 downto 0);
signal signalC : std_logic_vector(3 downto 0);
signal signalD : std_logic_vector(3 downto 0);
--sensor data signals
signal s_m : std_logic_vector(3 downto 0);
signal s_dm : std_logic_vector(3 downto 0);
signal s_cm : std_logic_vector(3 downto 0);
begin
--assigning components to output
uut3: seg_driver port map (
A => signalA,
B => signalB,
C => signalC,
D => signalD,
sevensegmentA => tsegA,
sevensegmentB => tsegB,
sevensegmentC => tsegC,
sevensegmentD => tsegD,
sevensegmentE => tsegE,
sevensegmentF => tsegF,
sevensegmentG => tsegG,
select_A => displayA,
select_B => displayB,
select_C => displayC,
select_D => displayD,
clock => clock);
uut4 : obstacle_detection_sensor PORT MAP(
fpgaclock => clock,
out_trigger => pin_trigger,
pulse => pin_pulse,
obstacle_in_m => s_m,
obstacle_in_dm => s_dm,
obstacle_in_cm => s_cm );
signalA <= s_cm;
signalB <= s_dm;
signalC <= s_m;
signalD <= "0000";
end Behavioral;
constraint:
<code>
##Clock signal
set_property IOSTANDARD LVCMOS33 [get_ports clock]
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} [get_ports clock]
##7 segment display
set_property IOSTANDARD LVCMOS33 [get_ports tsegA]
set_property IOSTANDARD LVCMOS33 [get_ports tsegB]
set_property IOSTANDARD LVCMOS33 [get_ports tsegC]
set_property IOSTANDARD LVCMOS33 [get_ports tsegD]
set_property IOSTANDARD LVCMOS33 [get_ports tsegE]
set_property IOSTANDARD LVCMOS33 [get_ports tsegF]
set_property IOSTANDARD LVCMOS33 [get_ports tsegG]
#set_property PACKAGE_PIN V7 [get_ports dp]
#set_property IOSTANDARD LVCMOS33 [get_ports dp]
set_property IOSTANDARD LVCMOS33 [get_ports displayA]
set_property IOSTANDARD LVCMOS33 [get_ports displayB]
set_property IOSTANDARD LVCMOS33 [get_ports displayC]
set_property IOSTANDARD LVCMOS33 [get_ports displayD]
##Pmod Header JC
##Sch name = JC1
set_property IOSTANDARD LVCMOS33 [get_ports pin_trigger]
##Sch name = JC2
set_property IOSTANDARD LVCMOS33 [get_ports pin_pulse]
set_property CLOCK_DEDICATED_ROUTE = "FALSE"; [get_ports pin_pulse]
##Sch name = JC3
#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
##Sch name = JC4
#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
##Sch name = JC7
#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
##Sch name = JC8
#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
##Sch name = JC9
#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
##Sch name = JC10
#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
set_property PACKAGE_PIN W5 [get_ports clock]
set_property PACKAGE_PIN P18 [get_ports pin_pulse]
set_property PACKAGE_PIN N17 [get_ports pin_trigger]
set_property PACKAGE_PIN U14 [get_ports displayA]
set_property PACKAGE_PIN V14 [get_ports displayB]
set_property PACKAGE_PIN U16 [get_ports displayD]
set_property PACKAGE_PIN V13 [get_ports displayC]
set_property PACKAGE_PIN W17 [get_ports tsegE]
set_property PACKAGE_PIN W16 [get_ports tsegF]
set_property PACKAGE_PIN V17 [get_ports tsegG]
set_property PACKAGE_PIN W14 [get_ports tsegA]
set_property PACKAGE_PIN W13 [get_ports tsegB]
set_property PACKAGE_PIN W15 [get_ports tsegC]
set_property PACKAGE_PIN V15 [get_ports tsegD]
</code>
<code>
##Clock signal
set_property IOSTANDARD LVCMOS33 [get_ports clock]
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} [get_ports clock]
##7 segment display
set_property IOSTANDARD LVCMOS33 [get_ports tsegA]
set_property IOSTANDARD LVCMOS33 [get_ports tsegB]
set_property IOSTANDARD LVCMOS33 [get_ports tsegC]
set_property IOSTANDARD LVCMOS33 [get_ports tsegD]
set_property IOSTANDARD LVCMOS33 [get_ports tsegE]
set_property IOSTANDARD LVCMOS33 [get_ports tsegF]
set_property IOSTANDARD LVCMOS33 [get_ports tsegG]
#set_property PACKAGE_PIN V7 [get_ports dp]
#set_property IOSTANDARD LVCMOS33 [get_ports dp]
set_property IOSTANDARD LVCMOS33 [get_ports displayA]
set_property IOSTANDARD LVCMOS33 [get_ports displayB]
set_property IOSTANDARD LVCMOS33 [get_ports displayC]
set_property IOSTANDARD LVCMOS33 [get_ports displayD]
##Pmod Header JC
##Sch name = JC1
set_property IOSTANDARD LVCMOS33 [get_ports pin_trigger]
##Sch name = JC2
set_property IOSTANDARD LVCMOS33 [get_ports pin_pulse]
set_property CLOCK_DEDICATED_ROUTE = "FALSE"; [get_ports pin_pulse]
##Sch name = JC3
#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
##Sch name = JC4
#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
##Sch name = JC7
#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
##Sch name = JC8
#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
##Sch name = JC9
#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
##Sch name = JC10
#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
set_property PACKAGE_PIN W5 [get_ports clock]
set_property PACKAGE_PIN P18 [get_ports pin_pulse]
set_property PACKAGE_PIN N17 [get_ports pin_trigger]
set_property PACKAGE_PIN U14 [get_ports displayA]
set_property PACKAGE_PIN V14 [get_ports displayB]
set_property PACKAGE_PIN U16 [get_ports displayD]
set_property PACKAGE_PIN V13 [get_ports displayC]
set_property PACKAGE_PIN W17 [get_ports tsegE]
set_property PACKAGE_PIN W16 [get_ports tsegF]
set_property PACKAGE_PIN V17 [get_ports tsegG]
set_property PACKAGE_PIN W14 [get_ports tsegA]
set_property PACKAGE_PIN W13 [get_ports tsegB]
set_property PACKAGE_PIN W15 [get_ports tsegC]
set_property PACKAGE_PIN V15 [get_ports tsegD]
</code>
##Clock signal
set_property IOSTANDARD LVCMOS33 [get_ports clock]
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} [get_ports clock]
##7 segment display
set_property IOSTANDARD LVCMOS33 [get_ports tsegA]
set_property IOSTANDARD LVCMOS33 [get_ports tsegB]
set_property IOSTANDARD LVCMOS33 [get_ports tsegC]
set_property IOSTANDARD LVCMOS33 [get_ports tsegD]
set_property IOSTANDARD LVCMOS33 [get_ports tsegE]
set_property IOSTANDARD LVCMOS33 [get_ports tsegF]
set_property IOSTANDARD LVCMOS33 [get_ports tsegG]
#set_property PACKAGE_PIN V7 [get_ports dp]
#set_property IOSTANDARD LVCMOS33 [get_ports dp]
set_property IOSTANDARD LVCMOS33 [get_ports displayA]
set_property IOSTANDARD LVCMOS33 [get_ports displayB]
set_property IOSTANDARD LVCMOS33 [get_ports displayC]
set_property IOSTANDARD LVCMOS33 [get_ports displayD]
##Pmod Header JC
##Sch name = JC1
set_property IOSTANDARD LVCMOS33 [get_ports pin_trigger]
##Sch name = JC2
set_property IOSTANDARD LVCMOS33 [get_ports pin_pulse]
set_property CLOCK_DEDICATED_ROUTE = "FALSE"; [get_ports pin_pulse]
##Sch name = JC3
#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
##Sch name = JC4
#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
##Sch name = JC7
#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
##Sch name = JC8
#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
##Sch name = JC9
#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
##Sch name = JC10
#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
set_property PACKAGE_PIN W5 [get_ports clock]
set_property PACKAGE_PIN P18 [get_ports pin_pulse]
set_property PACKAGE_PIN N17 [get_ports pin_trigger]
set_property PACKAGE_PIN U14 [get_ports displayA]
set_property PACKAGE_PIN V14 [get_ports displayB]
set_property PACKAGE_PIN U16 [get_ports displayD]
set_property PACKAGE_PIN V13 [get_ports displayC]
set_property PACKAGE_PIN W17 [get_ports tsegE]
set_property PACKAGE_PIN W16 [get_ports tsegF]
set_property PACKAGE_PIN V17 [get_ports tsegG]
set_property PACKAGE_PIN W14 [get_ports tsegA]
set_property PACKAGE_PIN W13 [get_ports tsegB]
set_property PACKAGE_PIN W15 [get_ports tsegC]
set_property PACKAGE_PIN V15 [get_ports tsegD]
I only get the result of display-D. Where is the problem?
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