uart between two fpga

i made a simple UART to communicate data between 2 fpga3 boards however both my transmitter and receiver modules are receiving data from computer not between each other

here is my modules i feel like there is a problem with receiver part in the Top module:

Plain text
Copy to clipboard
Open code in new window
EnlighterJS 3 Syntax Highlighter
<code>`timescale 1ns / 1ps
module Top_Module(
input clk,
input btn,
input transmit,
input reset,
input RxD,
input [7:0] data,
output reg TxD,
output TxD_Debug,
output transmit_debug,
output btn_debug,
output clk_debug,
output [7:0] RxData
);
wire transmitting_out;
assign Tx_Debug = TxD;
assign transmit_debug = transmitting_out;
assign btn_debug = reset;
assign clk_debug = clk;
Transmitter T1(clk, reset, transmit, data, TxD);
receiver R1(.clk_fpga(clk),.reset(reset),.RxD(RxD),.RxData(RxData));
Debounce_signals(clk,btn,transmitting_out);
endmodule
</code>
<code>`timescale 1ns / 1ps module Top_Module( input clk, input btn, input transmit, input reset, input RxD, input [7:0] data, output reg TxD, output TxD_Debug, output transmit_debug, output btn_debug, output clk_debug, output [7:0] RxData ); wire transmitting_out; assign Tx_Debug = TxD; assign transmit_debug = transmitting_out; assign btn_debug = reset; assign clk_debug = clk; Transmitter T1(clk, reset, transmit, data, TxD); receiver R1(.clk_fpga(clk),.reset(reset),.RxD(RxD),.RxData(RxData)); Debounce_signals(clk,btn,transmitting_out); endmodule </code>
`timescale 1ns / 1ps

module Top_Module(
    input clk,
    input btn,
    input transmit,
    input reset,
    input RxD,
    input [7:0] data,
    output reg TxD,
    output TxD_Debug,
    output transmit_debug,
    output btn_debug,
    output clk_debug,
    output [7:0] RxData
    );
    
    
    wire transmitting_out;

    assign Tx_Debug = TxD;
    assign transmit_debug = transmitting_out;
    assign btn_debug = reset;
    assign clk_debug = clk;
    
    Transmitter T1(clk, reset, transmit, data, TxD);
    receiver R1(.clk_fpga(clk),.reset(reset),.RxD(RxD),.RxData(RxData));
    Debounce_signals(clk,btn,transmitting_out);
endmodule

Plain text
Copy to clipboard
Open code in new window
EnlighterJS 3 Syntax Highlighter
<code>`timescale 1ns / 1ps
module Transmitter(
input clk,
input [7:0] data,
input transmit,
input reset,
output reg TxD
);
//INTERNAL VARIABLES
reg [3:0] bit_counter; //counts 10 bits
reg [13:0] baudrate_counter; //10415(counter= clk(100 Mhz)/BR(9600))
reg [9:0] shiftright_register; //ten bits serially transmitted from uart to board
reg state, next_state; //idle mode
reg shift; //shift the signal to start shifting the bits in the uart
reg load; //load signal to start loading the data into the shift right register & add start and stop bits
reg clear; //reset the bitcounter for uart transmission
//UART TRANSMISSION
always @(posedge clk)
begin
if (reset)
begin
state <= 0; //state is idle
bit_counter <= 0; //counter for bit transmission is reset to 0
baudrate_counter <= 0;
end
else
begin
baudrate_counter <= baudrate_counter + 1;
if (baudrate_counter == 10415)
begin
state <= next_state; //when state changes from idle to transmitting
baudrate_counter <= 0; //resetting counter
if (load) //if load is high
shiftright_register <= {1'b1, data, 1'b0}; //data is loaded into the register, 10 bits
if (clear) //if clear is high
bit_counter <= 0;
if (shift) //if shift signal is high
shiftright_register <= shiftright_register >> 1; //start shifting the data
bit_counter <= bit_counter + 1;
end
end
end
//mealy machine, state machine
always @(posedge clk)
begin
load <= 0; //setting load equal to zero
shift <= 0; //initially 0
clear <= 0; //initially 0
TxD <= 1; //when set to 1 there is no transmission in progress
case(state) //idle state
0: begin
if (transmit) //transmit button is pressed
begin
next_state <= 1; //goes to next state
load <= 1;
shift <= 0; //no shift here
clear <= 0; //to avoid clearing any counter
end
else
begin //if transmit button is not pressed
next_state <= 0; //idle
TxD <= 1; //no transmission
end
end
1: begin //transmit state
if (bit_counter == 10)
begin
next_state <= 0; //switching to idle mode
clear <= 1;
end
else
begin
next_state <= 1;
TxD <= shiftright_register[0]; //no transmission
shift <= 1;
end
end
default: next_state <= 0;
endcase
end
endmodule
</code>
<code>`timescale 1ns / 1ps module Transmitter( input clk, input [7:0] data, input transmit, input reset, output reg TxD ); //INTERNAL VARIABLES reg [3:0] bit_counter; //counts 10 bits reg [13:0] baudrate_counter; //10415(counter= clk(100 Mhz)/BR(9600)) reg [9:0] shiftright_register; //ten bits serially transmitted from uart to board reg state, next_state; //idle mode reg shift; //shift the signal to start shifting the bits in the uart reg load; //load signal to start loading the data into the shift right register & add start and stop bits reg clear; //reset the bitcounter for uart transmission //UART TRANSMISSION always @(posedge clk) begin if (reset) begin state <= 0; //state is idle bit_counter <= 0; //counter for bit transmission is reset to 0 baudrate_counter <= 0; end else begin baudrate_counter <= baudrate_counter + 1; if (baudrate_counter == 10415) begin state <= next_state; //when state changes from idle to transmitting baudrate_counter <= 0; //resetting counter if (load) //if load is high shiftright_register <= {1'b1, data, 1'b0}; //data is loaded into the register, 10 bits if (clear) //if clear is high bit_counter <= 0; if (shift) //if shift signal is high shiftright_register <= shiftright_register >> 1; //start shifting the data bit_counter <= bit_counter + 1; end end end //mealy machine, state machine always @(posedge clk) begin load <= 0; //setting load equal to zero shift <= 0; //initially 0 clear <= 0; //initially 0 TxD <= 1; //when set to 1 there is no transmission in progress case(state) //idle state 0: begin if (transmit) //transmit button is pressed begin next_state <= 1; //goes to next state load <= 1; shift <= 0; //no shift here clear <= 0; //to avoid clearing any counter end else begin //if transmit button is not pressed next_state <= 0; //idle TxD <= 1; //no transmission end end 1: begin //transmit state if (bit_counter == 10) begin next_state <= 0; //switching to idle mode clear <= 1; end else begin next_state <= 1; TxD <= shiftright_register[0]; //no transmission shift <= 1; end end default: next_state <= 0; endcase end endmodule </code>
`timescale 1ns / 1ps
module Transmitter(
    input clk,
    input [7:0] data,
    input transmit,
    input reset,
    output reg TxD
);

//INTERNAL VARIABLES
reg [3:0] bit_counter; //counts 10 bits
reg [13:0] baudrate_counter; //10415(counter= clk(100 Mhz)/BR(9600))
reg [9:0] shiftright_register; //ten bits serially transmitted from uart to board
reg state, next_state; //idle mode
reg shift; //shift the signal to start shifting the bits in the uart 
reg load; //load signal to start loading the data into the shift right register & add start and stop bits
reg clear; //reset the bitcounter for uart transmission

//UART TRANSMISSION
always @(posedge clk)
begin
    if (reset)
    begin
        state <= 0; //state is idle
        bit_counter <= 0; //counter for bit transmission is reset to 0
        baudrate_counter <= 0;
    end
    else
    begin
        baudrate_counter <= baudrate_counter + 1;
        if (baudrate_counter == 10415)
        begin
            state <= next_state; //when state changes from idle to transmitting
            baudrate_counter <= 0; //resetting counter
            if (load) //if load is high
                shiftright_register <= {1'b1, data, 1'b0}; //data is loaded into the register, 10 bits
            if (clear) //if clear is high
                bit_counter <= 0;
            if (shift) //if shift signal is high
                shiftright_register <= shiftright_register >> 1; //start shifting the data
            bit_counter <= bit_counter + 1;
        end
    end
end

//mealy machine, state machine
always @(posedge clk)
begin
    load <= 0; //setting load equal to zero
    shift <= 0; //initially 0
    clear <= 0; //initially 0
    TxD <= 1;   //when set to 1 there is no transmission in progress
    
    case(state) //idle state
        0: begin
            if (transmit) //transmit button is pressed
            begin
                next_state <= 1; //goes to next state
                load <= 1;
                shift <= 0; //no shift here
                clear <= 0; //to avoid clearing any counter
            end
            else
            begin //if transmit button is not pressed
                next_state <= 0; //idle
                TxD <= 1; //no transmission
            end
        end

        1: begin //transmit state
            if (bit_counter == 10)
            begin 
                next_state <= 0; //switching to idle mode
                clear <= 1;
            end
            else
            begin
                next_state <= 1;
                TxD <= shiftright_register[0]; //no transmission
                shift <= 1;
            end
        end

        default: next_state <= 0;
    endcase
end

endmodule

Plain text
Copy to clipboard
Open code in new window
EnlighterJS 3 Syntax Highlighter
<code>`timescale 1ns / 1ps
module receiver(
input clk_fpga,
input reset,
input RxD,
output [7:0] RxData
);
reg [3:0] bit_counter; //counts 10 bits
reg [13:0] baudrate_counter; //10415(counter= clk(100 Mhz)/BR(9600))
reg [9:0] rxshift_reg; //ten bits serially transmitted from uart to board
reg state, next_state; //idle mode
reg [1:0] sample_counter;
reg shift; //shift the signal to start shifting the bits in the uart
//reg load; //load signal to start loading the data into the shift right register & add start and stop bits
reg clear_bitcounter,inc_bitcounter,inc_samplecounter,clear_samplecounter; //reset the bitcounter for uart transmission
parameter clk_freq = 100_000_000;
parameter baud_rate = 9_400;
parameter div_sample = 4;
parameter div_counter = clk_freq /(baud_rate*div_sample);
parameter mid_sample = (div_sample/2);
parameter div_bit = 10;
assign RxData = rxshift_reg;
always @(posedge clk_fpga)
begin
if(reset)begin
state<=0;
bit_counter<=0;
baudrate_counter <=0;
sample_counter<=0;
end else begin
baudrate_counter<=baudrate_counter+1;
if(baudrate_counter>=div_counter-1)begin
baudrate_counter<=0;
state<= next_state;
if (shift) rxshift_reg <= rxshift_reg[9:1];
if(clear_samplecounter) sample_counter <=0;
if(inc_samplecounter) sample_counter<=sample_counter+1;
if(clear_bitcounter)bit_counter<=0;
if(inc_bitcounter)bit_counter<= bit_counter+1;
end
end
end
always @(posedge clk_fpga)
begin
shift<=0;
clear_samplecounter <=0;
inc_samplecounter <=0;
clear_bitcounter<=0;
inc_bitcounter<=0;
next_state<=0;
case(state)
0: begin
if(RxD)
begin
next_state<=0;
end
else begin
next_state<=1;
clear_bitcounter<=1;
clear_samplecounter<=1;
end
end
1: begin
next_state<=1;
if(sample_counter == mid_sample-1) shift<=1;
if(sample_counter == div_sample-1) begin
if(bit_counter == div_bit-1)begin
next_state<=0;
end
inc_bitcounter<=1;
clear_samplecounter<=1;
end else inc_samplecounter<=1;
end
default next_state <=1;
endcase
end
endmodule
</code>
<code>`timescale 1ns / 1ps module receiver( input clk_fpga, input reset, input RxD, output [7:0] RxData ); reg [3:0] bit_counter; //counts 10 bits reg [13:0] baudrate_counter; //10415(counter= clk(100 Mhz)/BR(9600)) reg [9:0] rxshift_reg; //ten bits serially transmitted from uart to board reg state, next_state; //idle mode reg [1:0] sample_counter; reg shift; //shift the signal to start shifting the bits in the uart //reg load; //load signal to start loading the data into the shift right register & add start and stop bits reg clear_bitcounter,inc_bitcounter,inc_samplecounter,clear_samplecounter; //reset the bitcounter for uart transmission parameter clk_freq = 100_000_000; parameter baud_rate = 9_400; parameter div_sample = 4; parameter div_counter = clk_freq /(baud_rate*div_sample); parameter mid_sample = (div_sample/2); parameter div_bit = 10; assign RxData = rxshift_reg; always @(posedge clk_fpga) begin if(reset)begin state<=0; bit_counter<=0; baudrate_counter <=0; sample_counter<=0; end else begin baudrate_counter<=baudrate_counter+1; if(baudrate_counter>=div_counter-1)begin baudrate_counter<=0; state<= next_state; if (shift) rxshift_reg <= rxshift_reg[9:1]; if(clear_samplecounter) sample_counter <=0; if(inc_samplecounter) sample_counter<=sample_counter+1; if(clear_bitcounter)bit_counter<=0; if(inc_bitcounter)bit_counter<= bit_counter+1; end end end always @(posedge clk_fpga) begin shift<=0; clear_samplecounter <=0; inc_samplecounter <=0; clear_bitcounter<=0; inc_bitcounter<=0; next_state<=0; case(state) 0: begin if(RxD) begin next_state<=0; end else begin next_state<=1; clear_bitcounter<=1; clear_samplecounter<=1; end end 1: begin next_state<=1; if(sample_counter == mid_sample-1) shift<=1; if(sample_counter == div_sample-1) begin if(bit_counter == div_bit-1)begin next_state<=0; end inc_bitcounter<=1; clear_samplecounter<=1; end else inc_samplecounter<=1; end default next_state <=1; endcase end endmodule </code>
`timescale 1ns / 1ps
module receiver(
    input clk_fpga,
    input reset,
    input RxD,
    output [7:0] RxData
    );
reg [3:0] bit_counter; //counts 10 bits
reg [13:0] baudrate_counter; //10415(counter= clk(100 Mhz)/BR(9600))
reg [9:0] rxshift_reg; //ten bits serially transmitted from uart to board
reg state, next_state; //idle mode
reg [1:0] sample_counter;
reg shift; //shift the signal to start shifting the bits in the uart 
//reg load; //load signal to start loading the data into the shift right register & add start and stop bits
reg clear_bitcounter,inc_bitcounter,inc_samplecounter,clear_samplecounter; //reset the bitcounter for uart transmission

parameter clk_freq = 100_000_000;
parameter baud_rate = 9_400;
parameter div_sample = 4;
parameter div_counter = clk_freq /(baud_rate*div_sample);
parameter mid_sample = (div_sample/2);
parameter div_bit = 10;

assign RxData = rxshift_reg;
always @(posedge clk_fpga)
begin
if(reset)begin
state<=0;
bit_counter<=0;
baudrate_counter <=0;
sample_counter<=0;
end else begin
baudrate_counter<=baudrate_counter+1;
if(baudrate_counter>=div_counter-1)begin
baudrate_counter<=0;
state<= next_state;
if (shift) rxshift_reg <= rxshift_reg[9:1];
if(clear_samplecounter) sample_counter <=0;
if(inc_samplecounter) sample_counter<=sample_counter+1;
if(clear_bitcounter)bit_counter<=0;
if(inc_bitcounter)bit_counter<= bit_counter+1;
end
end
end
always @(posedge clk_fpga)
begin
shift<=0;
clear_samplecounter <=0;
inc_samplecounter <=0;
clear_bitcounter<=0;
inc_bitcounter<=0;
next_state<=0;
case(state)
0: begin
if(RxD)
begin
next_state<=0;
end
else begin
next_state<=1;
clear_bitcounter<=1;
clear_samplecounter<=1;
end 
end
1: begin
next_state<=1;
if(sample_counter == mid_sample-1) shift<=1;
if(sample_counter == div_sample-1) begin
if(bit_counter == div_bit-1)begin
next_state<=0;
end
inc_bitcounter<=1;
clear_samplecounter<=1;
end else inc_samplecounter<=1;
end
default next_state <=1;
endcase
end
endmodule

with these modules normally two boards should receive and transmit data(8bit) between eachother.

Trang chủ Giới thiệu Sinh nhật bé trai Sinh nhật bé gái Tổ chức sự kiện Biểu diễn giải trí Dịch vụ khác Trang trí tiệc cưới Tổ chức khai trương Tư vấn dịch vụ Thư viện ảnh Tin tức - sự kiện Liên hệ Chú hề sinh nhật Trang trí YEAR END PARTY công ty Trang trí tất niên cuối năm Trang trí tất niên xu hướng mới nhất Trang trí sinh nhật bé trai Hải Đăng Trang trí sinh nhật bé Khánh Vân Trang trí sinh nhật Bích Ngân Trang trí sinh nhật bé Thanh Trang Thuê ông già Noel phát quà Biểu diễn xiếc khỉ Xiếc quay đĩa Dịch vụ tổ chức sự kiện 5 sao Thông tin về chúng tôi Dịch vụ sinh nhật bé trai Dịch vụ sinh nhật bé gái Sự kiện trọn gói Các tiết mục giải trí Dịch vụ bổ trợ Tiệc cưới sang trọng Dịch vụ khai trương Tư vấn tổ chức sự kiện Hình ảnh sự kiện Cập nhật tin tức Liên hệ ngay Thuê chú hề chuyên nghiệp Tiệc tất niên cho công ty Trang trí tiệc cuối năm Tiệc tất niên độc đáo Sinh nhật bé Hải Đăng Sinh nhật đáng yêu bé Khánh Vân Sinh nhật sang trọng Bích Ngân Tiệc sinh nhật bé Thanh Trang Dịch vụ ông già Noel Xiếc thú vui nhộn Biểu diễn xiếc quay đĩa Dịch vụ tổ chức tiệc uy tín Khám phá dịch vụ của chúng tôi Tiệc sinh nhật cho bé trai Trang trí tiệc cho bé gái Gói sự kiện chuyên nghiệp Chương trình giải trí hấp dẫn Dịch vụ hỗ trợ sự kiện Trang trí tiệc cưới đẹp Khởi đầu thành công với khai trương Chuyên gia tư vấn sự kiện Xem ảnh các sự kiện đẹp Tin mới về sự kiện Kết nối với đội ngũ chuyên gia Chú hề vui nhộn cho tiệc sinh nhật Ý tưởng tiệc cuối năm Tất niên độc đáo Trang trí tiệc hiện đại Tổ chức sinh nhật cho Hải Đăng Sinh nhật độc quyền Khánh Vân Phong cách tiệc Bích Ngân Trang trí tiệc bé Thanh Trang Thuê dịch vụ ông già Noel chuyên nghiệp Xem xiếc khỉ đặc sắc Xiếc quay đĩa thú vị
Trang chủ Giới thiệu Sinh nhật bé trai Sinh nhật bé gái Tổ chức sự kiện Biểu diễn giải trí Dịch vụ khác Trang trí tiệc cưới Tổ chức khai trương Tư vấn dịch vụ Thư viện ảnh Tin tức - sự kiện Liên hệ Chú hề sinh nhật Trang trí YEAR END PARTY công ty Trang trí tất niên cuối năm Trang trí tất niên xu hướng mới nhất Trang trí sinh nhật bé trai Hải Đăng Trang trí sinh nhật bé Khánh Vân Trang trí sinh nhật Bích Ngân Trang trí sinh nhật bé Thanh Trang Thuê ông già Noel phát quà Biểu diễn xiếc khỉ Xiếc quay đĩa
Thiết kế website Thiết kế website Thiết kế website Cách kháng tài khoản quảng cáo Mua bán Fanpage Facebook Dịch vụ SEO Tổ chức sinh nhật