Outputs of test bench don’t change in modelsim(vhdl)
i have a problem where my main code works(i have simulated it in quartus) and the test bench look ok as well, but for some reason when i run the test bench in modelsim the outputs don’t change
i have a problem where my main code works(i have simulated it in quartus) and the test bench look ok as well, but for some reason when i run the test bench in modelsim the outputs don’t change