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Tag Archive for vhdlmodularity

Drive a signal decalred in package from a procedure declared in another package

I am trying to drive signal “sig1” (std_logic) from a process in test bench. The singal declaration is in a package “A” placed in âlibrary “lib1”. There is another package “B” in library “lib2” ,where i have written a procedure “proc1” which need to drive this singal “sig1”. The procedure call in in a process in the test bench. I can sucessfully read this signal “sig1” in test bench but cannot drive this.