Counter output not synchronized to clk in vhdl in real fpga
I am trying to figure out why there is instable output of simple counter. I am using Sipeed Tang Primer 20k development board based on GW2A-LV18PG256C8/I7 FPGA. I created simple project, which uses clock divider to get output clock ~5.5 Mhz from input 27 Mhz global clock.
My Pulse DEbouncer is producing two pulses each time i press a key
Im trying to use a debouncer for my project but when i test it out and click on a key it send a pulse when i click down and when i release a button. How can i fix this?
When should I use a function over a procedure? [VHDL]
I’ve been trying to understand when to use a Function and when to use a Procedure in VHDL. From my understanding both are Synthesizable. You use a Function when you have 1 return value and a Procedure when you have multiple outputs. My question is why don’t I just use a procedure all the time (1 output or many outputs)?