VHDL when else interpretation
Is it correct to have such a code where the output depends on three input signals, but the signal C is not relevant in each case? So I do not specify this C in every case.
VHDL immediate conversion unit
I am trying to write a data path in VHDL and I’m struggling with the part of the immediate instructions where I have to take the 16 bit immediate part of the instruction and convert it to a 32 bit and also shift it left by 2 or 16 depending on the Opcode of the instruction. I decided to do this with a FSM. this is the code i have written so far:
IF statement in vhdl within a process
This is supposed to be an if statement. What really matters here is the byte_count. When it reaches 6, it is going to execute the instructions in the elsif. However, the problem is that the if statement is within a process, so the transition to the next state will occur only on the next clock cycle. The state will remain in the preamble state, and it will enter the if statement again, sending the PREAMBLE_PATTERN again before transitioning to STREAM. How can I handle that?