I was wondering what is the difference between

Say I have the following type definitions:

I have hundreds of VHDL files and Quartus 24.2 decided to raise errors for hundreds of lines.

So, this code was given to me to fix, and it made me wonder how it actually should work. The key pitfall here is multiple IF statements in a process that sets/clears the same output. So which one “wins”?

I designed a down counter with a clk, set_n, load_data, and timer_on. When I put set_n = 0, the down counter is supposed to load_data, set the timer_on = 1, and then keep decreasing the counter until it reaches 0. However, the simulation does not show that my down_counter is working.

I have a question about how write a function cross entropy binary in vhdl the last is
L= -(y*log (ypred)+(1-y)*log(1-ypred) the problem is how can write a log in VHDL , sorry about my English thanks

I’m having trouble understanding the difference between or the use of instantiating components instead of directly using an array or std_logic_vector().

In line 99, i concatenated keyval1 and keyval2 to get a 16 bit xkey signal.

I wanted to ask about how to read machine code as assembly code. I have only done convertions that looks like this

I want to make a 16-bit multiplier. The way it works is that I take two 32-bit numbers from the input and multiply them with the least valuable 16 bits and give them to the output, and I also use a 32-bit adder. In every clock, the multiplier shifts right and the multiplicand shifts left, and after 16 clocks, the output is ready, but the output is always zero.
Of course, the 32-bit adder works correctly.