Modeling a D-type Flip Flop in Verilog with gate-level modeling vs. behavioral modeling seems to result in state transitions happening at different edges of the clock signal. I’m sure I’m missing something, so looking for some guidance. With a gate-level model, there are two internal D Latches (at least the way I’m doing it) with the second (output) latch having an inverted clock signal. On the positive edge, the first latch picks up the input, and on the negative edge the second latch propagates the input to the output. With a behavioral model (triggering on posedge) the output of the latch seems to transition instantly on the positive edge. These seem to be two very different outcomes. This is when doing simulation via iverilog or Vivado.