Debugging a VHDL & Systemverilog simple example for using SVA’s. incomprehensible Z’s and X’s values
I created an simple flipflop instance and testbench, with VHDL.
Besides I wanted to use the property assertions in systemverilog for degugging. Despite the sva errors work correctly, being report at the correct time, I would like to know how to debug this property assertions. And also why what I see, is in the wave signals and inputs in the .sv files, present always a value of X.