having trouble with the undefined clock and signal output of a testbench of an AM modulation project written in VHDL
I’ve been recently working on an AM modulation module written in VHDL, and I have made this reference model in Simulink to set the parameters of the fixed-point model based on comparing it with the output of the floating-point model.
AM modulation output
yellow:fixed-point,blude:floating-point
reference model for floating-point and fixed-point