I’m a beginner in FPGA programming and I’m trying to implement a noise filter in Verilog on Vivado. Right now my project failed timing due to negative slack (WNS=-15ns). I’m trying to run around 100 kHz by doing calculations every 1024 clock cycles with a 125 MHz clock (code below). I understand that my calculations take too long for a clock cycle, and it’s specifically the x_next calculation at the moment that is taking the longest time. I cannot pipeline my calculations any more because all variables are dependent on the previous one, so they need to be evaluated sequentially. I thought about setting a multicycle path but I’m not that advanced yet in FPGA programming so I’m not sure if I can do it. Does anyone have any other suggestions on how I can make my calculations run faster?

I’m a beginner in FPGA programming and I’m trying to implement a noise filter in Verilog on Vivado. I want to operate at 100 kHz and I’m doing that by doing my calculations every 1024 clock cycles with a 125 MHz clock. For this, I have a counter and a counter1024 that resets every 1024 cycles. When I synthesize my design, I get an error “[Synth 8-6858] multi-driven net Q[31] is connected to at least one constant driver which has been preserved, other driver is ignored” which I guess is due to defining something wrong, but I can’t figure out what the problem is because logically it should be updating correctly and the line that gives an error is not a line I added. Does anyone have any suggestions on how I could fix this error?