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Verilog code for Booth’s multiplication algorithm has issues. Can anyone tell why “temp” is getting zero value?

module Booth_alg( output [15:0]result, output reg [15:0]temp, output reg [2:0]count,c1,cnt, input clk,rst, input [7:0]M,Q); reg [15:0]mult; reg [7:0]m; always@(*) m=(~M)+1’b1; always@(posedge clk) begin if(rst) begin count<=3’d7; cnt<=0; c1<=3’d0; {temp,mult}<=32’d0; end else begin count<=count-1; if((Q[count] ^ Q[count-1]) == 1’b1) begin cnt<=count; c1<=c1+1; if((c1%2)==1) temp<={8’b00000000,M}; else temp<={{8{m[7]}},m}; temp<=temp<<cnt; mult<=mult+temp; end else begin cnt<=cnt; c1<=c1; temp<=0; mult<=mult; end […]

I wrote a Verilog code for Booth’s multiplication algorithm but facing issues. Can anyone tell why “temp” is getting zero value?

module Booth_alg( output [15:0]result, output reg [15:0]temp, output reg [2:0]count,c1,cnt, input clk,rst, input [7:0]M,Q); reg [15:0]mult; reg [7:0]m; always@(*) m=(~M)+1’b1; always@(posedge clk) begin if(rst) begin count<=3’d7; cnt<=0; c1<=3’d0; {temp,mult}<=32’d0; end else begin count<=count-1; if((Q[count] ^ Q[count-1]) == 1’b1) begin cnt<=count; c1<=c1+1; if((c1%2)==1) temp<={8’b00000000,M}; else temp<={{8{m[7]}},m}; temp<=temp<<cnt; mult<=mult+temp; end else begin cnt<=cnt; c1<=c1; temp<=0; mult<=mult; end […]