I am new to verilog and i am getting these errors in quartus prime
this is my module..
reg [2:0]count=3’b0;
reg [l4_offset-1:0]offset; wire [l4_offset-1:0]pseudo_offset;
Verilog code output is always zzz using carry lookahead adder
I am trying to make a multiplier using carry lookahead adder. But the half of my output is zzzz. Here is a part of my code. The cla16 is a 16 bit carry lookahead adder. It is producing zz at output in v16bit module.