I have 2 STM32F407 processors talking via SPI. The slave monitors many inputs, when something of interest happens it interrupts the master which starts the SPI transfer. This process is register based (NO HAL) and 100% driven by interrupts and DMA and everything works as it should. The problem is when SPI CRC is added. The Reference Manual RM0090 Rev 19 pages 891 and 892 provide CRC configuration details. It indicates (I think) that the NSS line needs to be held low at least into the beginning of the CRC transmission. See steps 5 and 6 page 892.