Is memory barrier NECESSARY for memory consistency?
After reading Memory Barriers: a Hardware View for Software Hackers, I came up with a point which I am not sure of its correctness, as posted in the title.
I came up with this point because of intuition from the CPU cache level (which I am not sure of either): as the MESI protocol and its families guarantee coherence, memory consistency requires memory fences to synchronize across multiple processors, and this requirement would reflect into the programming language internals.
Is memory barriers NECESSARY for memory consistency?
After reading Memory Barriers: a Hardware View for Software Hackers, I came up with a point which I am not sure of its correctness, as posted in the title.
I came up with this point because of intuition from the CPU cache level (which I am not sure of either): as the MESI protocol and its families guarantee coherence, memory consistency requires memory fences to synchronize across multiple processors, and this requirement would reflect into the programming language internals.
Are All Memory Consistency Guarantees Implemented Through Memory Barriers?
After reading Memory Barriers: a Hardware View for Software Hackers, I came up with a point which I am not sure of its correctness, as posted in the title.
I came up with this point because of intuition from the CPU cache level (which I am not sure of either): as the MESI protocol and its families guarantee coherence, memory consistency requires memory fences to synchronize across multiple processors, and this requirement would reflect into the programming language internals.