VHDL Synthesis ERROR: [Synth 8-27] else clause after check for clock not supported
I’m trying to build a clock divider based on integer counters. the simulation works correctly but the synthesis fails with the error above and marks line 25.
I don’t understand the reason why it isn’t synthesizable. Thank you for your help.
ERROR: [Synth 8-27] else clause after check for clock not supported
I’m trying to build a clock divider based on integer counters. the simulation works correctly but the synthesis fails with the error above and marks line 25.
I don’t understand the reason why it isn’t synthesizable. Thank you for your help.