In a RISC-V architecture, do jump instructions (conditional or JAL/JALR) increase the PC by 4 as the rest of the instructions?
I’m working on a RISC-V CPU emulator and have all instructions implemented. The thing is that I’m not sure if the jumps are failing. This is the current implementation I have for BGEU to make an example:
In a RISC-V architecture, does jump instructions (conditional or JAL/JALR) increase de PC by 4 as the rest of the instructions?
I’m working on a RISC-V CPU emulator and have all instructions implemented. The thing is that I’m not sure if the jumps are failing. This is the current implementation I have for BGEU to make an example: