I have produced an IP for a custom board with a ZYNQ based SoC. The IP is pretty simple, having an AXI-LITE interface to setup some registers. The AXI interface is of course connected to the ZYNQ processor system through an AXI interconnect/bridge. Those registers in hand are used by an FSM in order for the FSM to send signals to several different peripherals of which some are routedd outside the FPGA (LEDs, opto-couplers, relays, IEPE, etc…) and some stay inside (XADC, other IP activation,etc…).