Memory bandwidth iterating through array and prefetching
I’m trying to understand the throughput of iterating over an array with varying sizes N.
If cacheline is 128bytes or 256bytes that is longer than burst 64bytes.What happens to DDR？
Cacheline size usually is 64 bytes, DDR data line bit width is 64 bits and burst length is 8, a burst transaction is 64 bytes which is equal to cacheline size.
But if cacheline size is 128bytes or 256bytes, What happens to DDR when cacheline miss.
How to store bytes into SRAM (Cache memory)
Is there any instruction on assembly that allocates memory in the SRAM of any level? Is that possible?