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Why does the BSWAP x86-64 instruction have latency 2 on modern Intel processors?

The 64-bit BSWAP instruction is listed to have a latency of 2 cycles on both uops.info and in Agner Fog’s instruction tables on modern Intel architectures like Broadwell, Cannon Lake, Ice Lake, etc. On AMD this instruction has been a single-cycle latency instruction for a very, very long time according to these sources.