Does the Cortex-M55 Processor Support Shareable and Cacheable Attributes Simultaneously?
I was looking at the Cortex-M55 TRM document and came across the following statement:
When to manually set the T bit of EPSR?
I’m new to ARMv6-M architecture. I understand that the T bit of EPSR must always be 1 to indicate Thumb state. Looks like the compiler will take care of this most of the time, but are there any situations where I should manually set the T bit of EPSR?