Say I have the multidimensional bus

wire logic [7:0]example_bus[60] [16][4];

and a module has the output

output logic [7:0]example_out[16][4];

How would I assign example_out to all 60 wires in example_bus?

I know how to assign it to individual wires.

example_mod example_mod1(
.example_out(example_bus[0]));

But I can’t work out how to assign the output to the whole bus.

I have considered using a seperate assignment but I find that usually causes timing problems.