I have a class in SystemVerilog that represents an abstract data transaction in my system. It looks something like this:

class #(param BIT_DEPTH) MyData;
    logic [BIT_DEPTH-1:0] thedata [];
    metadata_type_t some_info_about_thedata;
    
    //...
endclass

I want to put a bunch of my_data with different BIT_DEPTHS together into a queue, but obviously this won’t work.

I tried inheriting from a base class…

class MyBaseData;
    int bit_depth;
endclass

class #(param BIT_DEPTH) MyData extends MyBaseData;
    logic [BIT_DEPTH-1:0] thedata [];
    metadata_type_t some_info_about_thedata;
    
    function new(metadata_type_t md);
        this.bit_depth = BIT_DEPTH;
        this.some_info_about_thedata = md;
        this.thedata = new[some_info_about_thedata.thedatasize];
    endfunction
endclass

But obviously this doesn’t work: I can’t make an object with unknown parameter values at runtime:

    MyBaseData mbd = queue.pop_back();
    MyData#(mbd.bit_depth) mydata;         // obviously not allowed
    $cast(mydata, mbd);

What I really want is to have a packed logic datatype whose width is only known at runtime.

Any workaround for this?