My SystemVerilog is a little bit rusty and I’m trying to reaccquaint myself with it. I have some RTL that looks like this:
<code>typedef logic node;
typedef struct packed {
node a;
node b;
} type1;
module foo(type1 sig);
...
endmodule
</code>
<code>typedef logic node;
typedef struct packed {
node a;
node b;
} type1;
module foo(type1 sig);
...
endmodule
</code>
typedef logic node;
typedef struct packed {
node a;
node b;
} type1;
module foo(type1 sig);
...
endmodule
Module foo is instantiated like this:
<code>foo u0(.sig('{1'b1, 1'b0}));
</code>
<code>foo u0(.sig('{1'b1, 1'b0}));
</code>
foo u0(.sig('{1'b1, 1'b0}));
Questions:
-
I understand {1’b1, 1’b0} is concatenation of two bits. But what is the meaning of the single tick before {}?
-
This type of RTL compiles ok in Synopsys VCS, but when I try to read it in with Synopsys Fusion Compiler, it is giving me an error indicating:
The construct ‘assignment pattern in port connection’ is not supported.
The tool does not like the ‘{} assigment. How should I adjust the RTL to resolve this error?