I compile the silly function f(a,b,c) = sum minterms(0,4,5) in systemverilog design file
and the netlist rtl viewer shows me a weird gate schematic ~a&~b&~c + (a&~b)&c + (a&~b)&c
instead of displaying the proper reduced gate schematic ~b&~c + a&~b. I don’t know why this weird overcomplex result. I admit I’m just beginning but I dismay when following the book the result doesn’t look like the expected one at all. (By the way the book is Digital Design and Computer Architecture by Harris and Harris).