I have a legacy project based on an Infineon/Cypress PSoC4 micro. I am attempting to port it to a new Infineon/Cypress part (PSoC4 MAX). The project is an I2C slave that communicates with an I2C master that sends out periodic (3x/second) pings to the device containing the slave address. The master also sends specific commands to the slave when the user (say, me) requests.

The slave device is configured to accept the slave address in the RX FIFO:

const cy_stc_scb_i2c_config_t CYBSP_SCB_I2C_config =
{
    .i2cMode = CY_SCB_I2C_SLAVE,
    .useRxFifo = true,
    .useTxFifo = true,
    .slaveAddress = 0x58,
    .slaveAddressMask = 0xFE,
    .acceptAddrInFifo = true,
    .ackGeneralAddr = false,
    .hsEnable = false,
    .enableWakeFromSleep = true,
    .enableDigitalFilter = false,
    .lowPhaseDutyCycle = 0,
    .highPhaseDutyCycle = 0,
}; 

The issue I am having is that my firmware buffer is getting filled with these slave addresses that are arriving periodically, and the commands I am trying to send get lost in the sea of these addresses. This does NOT happen with the legacy project (which uses some older I2C library code).

I guess my question is how one would think the library code to handle the receipt of these slave addresses SHOULD work: the address needs to be ack’d to the master, but at some point I would think these address packets should be “consumed”. I’d actually think they shouldn’t get copied from the hardware buffer into the firmware buffer, but they are.

This is the ISR code:

/*******************************************************************************
* Function Name: Cy_SCB_I2C_SlaveInterrupt
****************************************************************************//**
*
* This is the interrupt function for the SCB configured in I2C mode as the
* slave. This function should be called inside the user-defined interrupt
* service routine to make any of the slave functions to work.
*
* param base
* The pointer to the I2C SCB instance.
*
* param context
* The pointer to the context structure ref cy_stc_scb_i2c_context_t allocated
* by the user. The structure is used during the I2C operation for internal
* configuration and data retention. The user must not modify anything
* in this structure.
*
*******************************************************************************/
void Cy_SCB_I2C_SlaveInterrupt(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
{
uint32_t slaveIntrStatus;

bool slaveAddrInFifo = false;

/* Handle an I2C wake-up event */
if (0UL != (CY_SCB_I2C_INTR_WAKEUP & Cy_SCB_GetI2CInterruptStatusMasked(base)))
{
    /* Move from IDLE state, the slave was addressed. Following address match
    * interrupt continue transfer.
    */
    context->state = CY_SCB_I2C_SLAVE_ACTIVE;

    Cy_SCB_ClearI2CInterrupt(base, CY_SCB_I2C_INTR_WAKEUP);
}

/* Handle the slave interrupt sources */
slaveIntrStatus = Cy_SCB_GetSlaveInterruptStatusMasked(base);

/* Handle the error conditions */
if (0UL != (CY_SCB_I2C_SLAVE_INTR_ERROR & slaveIntrStatus))
{
    /* Update the status */
    context->slaveStatus |= (0UL != (CY_SCB_SLAVE_INTR_I2C_BUS_ERROR & slaveIntrStatus)) ?
                                        CY_SCB_I2C_SLAVE_BUS_ERR : CY_SCB_I2C_SLAVE_ARB_LOST;

    /* Disable the RX interrupt source to drop data into RX FIFO if any */
    Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);

    /* Add the stop status to back into the default state and set completion statuses */
    slaveIntrStatus |= CY_SCB_SLAVE_INTR_I2C_STOP;
}
else
{
    if (0UL != (CY_SCB_SLAVE_INTR_I2C_STOP & slaveIntrStatus))
    {
        /* Get data from the RX FIFO after a stop is generated if there is
        * space to store it.
        */
        if ((Cy_SCB_GetNumInRxFifo(base) > 0UL) && (context->slaveRxBufferSize > 0UL))
        {
            Cy_SCB_SetRxInterrupt    (base, CY_SCB_RX_INTR_LEVEL);
            Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL);
        }
    }
}

/* Handle the receive direction (master writes data) */
if (0UL != (CY_SCB_RX_INTR_LEVEL & Cy_SCB_GetRxInterruptStatusMasked(base)))
{
    /* Check if SCB configured to accept the slave address in the RX FIFO */
    if (_FLD2BOOL(SCB_CTRL_ADDR_ACCEPT, SCB_CTRL(base)))
    {
    #ifndef CY_IP_MXSCB
        /* Delay is needed for M0S8SCB only */
        if (context->delayInFifoAddress > 0UL)
        {
            /* Wait one HIGH period of the SCL clock. */
            Cy_SysLib_DelayUs(context->delayInFifoAddress);
        }
    #endif /* CY_IP_MXSCB */

        slaveAddrInFifo = (0UL != (CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH &
                                Cy_SCB_GetSlaveInterruptStatusMasked(base)));
    }

    /* Process data bytes, but skip processing in case slave address is in RX FIFO.
    *  Leave the address to be processed by the function SlaveHandleAddress().
    */
    if (!slaveAddrInFifo)
    {
        SlaveHandleDataReceive(base, context);

        Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL);
    }
}

/* Handle the transfer completion */
if (0UL != (CY_SCB_SLAVE_INTR_I2C_STOP & slaveIntrStatus))
{
    SlaveHandleStop(base, slaveAddrInFifo, context);

    Cy_SCB_ClearSlaveInterrupt(base, CY_SCB_SLAVE_INTR_I2C_STOP);

    /* Update the slave interrupt status */
    slaveIntrStatus = Cy_SCB_GetSlaveInterruptStatusMasked(base);
}

/* Handle the address reception */
if (0UL != (CY_SCB_I2C_SLAVE_INTR_ADDR & slaveIntrStatus))
{
    SlaveHandleAddress(base, context);

    Cy_SCB_ClearI2CInterrupt(base, CY_SCB_I2C_INTR_WAKEUP);
    Cy_SCB_ClearSlaveInterrupt(base, CY_SCB_I2C_SLAVE_INTR_ADDR);
}

/* Handle the transmit direction (master reads data) */
if (0UL != (CY_SCB_I2C_SLAVE_INTR_TX & Cy_SCB_GetTxInterruptStatusMasked(base)))
{
    SlaveHandleDataTransmit(base, context);

    Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_LEVEL);
}
}

This is the function that should handle receiving the slave address in the buffer:

/*******************************************************************************
* Function Name: SlaveHandleAddress
****************************************************************************//**
*
* Prepares the slave for the following Read or Write transfer after the
* matched address was received.
*
* param base
* The pointer to the I2C SCB instance.
*
* param context
* The pointer to the context structure ref cy_stc_scb_i2c_context_t allocated
* by the user. The structure is used during the I2C operation for internal
* configuration and data retention. The user must not modify anything
* in this structure.
*
*******************************************************************************/
static void SlaveHandleAddress(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
{
    /* The default command is the ACK address. It can be overridden in an address callback */
    cy_en_scb_i2c_command_t cmd = CY_SCB_I2C_ACK;

    /* The callback for the address in RX FIFO or a general call */
    if (NULL != context->cbAddr)
    {
        uint32_t events = 0UL;

        /* Set an address in the FIFO event if the address accept is enabled */
        if (_FLD2BOOL(SCB_CTRL_ADDR_ACCEPT, SCB_CTRL(base)))
        {
            events = (0UL != (CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH & Cy_SCB_GetSlaveInterruptStatusMasked(base))) ?
                          CY_SCB_I2C_ADDR_IN_FIFO_EVENT : 0UL;
        }

        /* Set a general call event if "ignore general call" is disabled */
        if (!_FLD2BOOL(SCB_I2C_CTRL_S_GENERAL_IGNORE, SCB_I2C_CTRL(base)))
        {
            events |= (0UL != (CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR & Cy_SCB_GetSlaveInterruptStatusMasked(base))) ?
                           CY_SCB_I2C_GENERAL_CALL_EVENT : 0UL;
        }

        /* Check presence of events before involve callback */
        if (0UL != events)
        {
            /* Involve a callback for the address phase and get the ACK/NACK command */
            cmd = context->cbAddr(events);

            /* Clear RX level interrupt after address reception */
            Cy_SCB_ClearRxInterrupt(base, CY_SCB_RX_INTR_LEVEL);

            if (cmd == CY_SCB_I2C_ACK)
            {
                /* Clear the stall stop status and enable the stop interrupt source */
                Cy_SCB_ClearSlaveInterrupt(base, CY_SCB_SLAVE_INTR_I2C_STOP);
            }
            else if (cmd == CY_SCB_I2C_NAK)
            {
                /* Disable the stop interrupt source */
                Cy_SCB_SetSlaveInterruptMask(base, CY_SCB_I2C_SLAVE_INTR_NO_STOP);
            }
            else
            {
                /* For wait command no need to configure the interrupts here. */
            }
        }
    }

    /* Clear the TX FIFO before continue the transaction */
    Cy_SCB_ClearTxFifo(base);

    /* Checking for callback return status before sending ACK/NACK */
    if(cmd != CY_SCB_I2C_WAIT)
    {
        /* Set the command to an ACK or NACK address */
        SCB_I2C_S_CMD(base) |= (cmd == CY_SCB_I2C_ACK) ? SCB_I2C_S_CMD_S_ACK_Msk : SCB_I2C_S_CMD_S_NACK_Msk;
    }

    if (cmd == CY_SCB_I2C_ACK)
    {
        SlaveHandleAck(base, context);
    }
}

The last part (I think) is the ACK handle code:

/*******************************************************************************
* Function Name: SlaveHandleAck
****************************************************************************//**
*
* Prepares the buffers and FIFO for the Read or Write transfer after the
* matched address was received and ACK sent by the slave.
*
* param base
* The pointer to the I2C SCB instance.
*
* param context
* The pointer to the context structure ref cy_stc_scb_i2c_context_t allocated
* by the user. The structure is used during the I2C operation for internal
* configuration and data retention. The user must not modify anything
* in this structure.
*
*******************************************************************************/
static void SlaveHandleAck(CySCB_Type *base, cy_stc_scb_i2c_context_t *context)
{
bool readDirection = _FLD2BOOL(SCB_I2C_STATUS_S_READ,SCB_I2C_STATUS(base));

/* Notify the user about start of transfer */
if (NULL != context->cbEvents)
{
    context->cbEvents(readDirection ? CY_SCB_I2C_SLAVE_READ_EVENT : CY_SCB_I2C_SLAVE_WRITE_EVENT);
}

/* Prepare for a transfer */
if (readDirection)
{
    context->state        = CY_SCB_I2C_SLAVE_TX;
    context->slaveStatus |= CY_SCB_I2C_SLAVE_RD_BUSY;

    /* Prepare to transmit data */
    context->slaveTxBufferIdx = context->slaveTxBufferCnt;
    context->slaveRdBufEmpty  = false;
    Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL);
}
else
{
    uint32_t level = 0UL;

    context->state        = CY_SCB_I2C_SLAVE_RX;
    context->slaveStatus |= CY_SCB_I2C_SLAVE_WR_BUSY;

    /* Prepare to receive data */
    Cy_SCB_SetRxInterruptMask(base, CY_SCB_RX_INTR_LEVEL);

    if (context->useRxFifo)
    {
        if (context->slaveRxBufferSize > 0UL)
        {
            /* ACK data automatically until RX FIFO is full */
            SCB_I2C_CTRL(base) |= SCB_I2C_CTRL_S_READY_DATA_ACK_Msk;

            if (context->slaveRxBufferSize > CY_SCB_I2C_FIFO_SIZE)
            {
                /* Set a level in RX FIFO to trigger the receive interrupt source */
                level = (context->slaveRxBufferSize - CY_SCB_I2C_FIFO_SIZE);
                level = ((level > CY_SCB_I2C_FIFO_SIZE) ? (CY_SCB_I2C_FIFO_SIZE / 2UL) : level) - 1UL;
            }
            else
            {
                /* Set a level in RX FIFO to read the number of bytes */
                level = (context->slaveRxBufferSize - 1UL);

                /* NACK when RX FIFO becomes full */
                SCB_I2C_CTRL(base) |= SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk;

                /* Disable the RX level interrupt and wait until RX FIFO is full or stops */
                Cy_SCB_SetRxInterruptMask(base, CY_SCB_CLEAR_ALL_INTR_SRC);
            }
        }
    }

    Cy_SCB_SetRxFifoLevel(base, level);
}
}

Can anyone explain to me if I should expect the slave addresses to be copied into the FW buffer, or how these packets are otherwise consumed?