I am just starting to learn Quartus and verilog as a whole, and working on a data bank project which uses the following code:

Top module:

`timescale 1ns / 1ps
module TopLab #(
    parameter BIT_ADDR = 4,
    parameter BIT_DATO = 8
)(
    input [BIT_ADDR-1:0] AddrRa,
    input [BIT_ADDR-1:0] AddrRb,
    output [BIT_DATO-1:0] DatOutRa,
    output [BIT_DATO-1:0] DatOutRb,
    input [BIT_ADDR-1:0] AddrW,
    input [BIT_DATO-1:0] DatW,
    output [0:6] sSeg,
    output [3:0] An,
    input RegWrite,
    input Clk,
    input Rst
);

    reg [15:0] num = 0;

    // Instancia del módulo BancoRegistro
    BancoRegistro #(.BIT_ADDR(BIT_ADDR), .BIT_DATO(BIT_DATO))
        bancoregistro (
            .addrRa(AddrRa),
            .addrRb(AddrRb),
            .datOutRa(DatOutRa),
            .datOutRb(DatOutRb),
            .addrW(AddrW),
            .datW(DatW),
            .RegWrite(RegWrite),
            .clk(Clk),
            .rst(Rst)
        );

    // Instancia del módulo display
    display display_inst (
        .num(num),
        .clk(Clk),
        .sseg(sSeg),
        .an(An),
        .rst(Rst)
    );

    always @(posedge Clk) begin
        if (Rst == 0) begin
            num <= 0;
        end else begin
            num[15:8] <= DatOutRa;
            num[7:0] <= DatOutRb;
        end
    end

endmodule

7 segment display:

`timescale 1ns / 1ps
module display(
    input [15:0] num,
    input clk,
    output [0:6] sseg,
    output reg [3:0] an,
     input rst
    );



reg [3:0]bcd=0;
 
BCDtoSSeg bcdtosseg(.BCD(bcd), .SSeg(sseg));

reg [26:0] cfreq=0;
wire enable;

// Divisor de frecuecia

assign enable = cfreq[16];
assign led = enable;
always @(posedge clk) begin
  if(rst==0) begin
        cfreq <= 0;
    end else begin
        cfreq <=cfreq+1;
    end
end

reg [1:0] count =0;
always @(posedge enable) begin
        if(rst == 0) begin
            count<= 0;
            an<=4'b1111; 
        end else begin 
            count<= count+1;
            an<=4'b1101; 
            case (count) 
                2'h0: begin bcd <= num[3:0];   an<=4'b1110; end 
                2'h1: begin bcd <= num[7:4];   an<=4'b1101; end 
                2'h2: begin bcd <= num[11:8];  an<=4'b1011; end 
                2'h3: begin bcd <= num[15:12]; an<=4'b0111; end 
            endcase
        end
end

endmodule

Register bank

`timescale 1ns / 1ps

module BancoRegistro #(              //   #( Parametros
         parameter BIT_ADDR = 4,  //   BIT_ADDR Número de bit para la dirección
         parameter BIT_DATO = 8  //  BIT_DATO  Número de bit para el dato
    )
    (
    input [BIT_ADDR-1:0] addrRa,
    input [BIT_ADDR-1:0] addrRb,
    
     output [BIT_DATO-1:0] datOutRa,
    output [BIT_DATO-1:0] datOutRb,
    
     input [BIT_ADDR-1:0] addrW,
    input [BIT_DATO-1:0] datW,
    
     input RegWrite,
    input clk,
    input rst
    );

// La cantdiad de registros es igual a: 
localparam NREG = 2 ** BIT_ADDR;

integer i = 0;
  
//configiración del banco de registro 
reg [BIT_DATO-1: 0] breg [NREG-1:0];


assign  datOutRa = breg[addrRa];
assign  datOutRb = breg[addrRb];

always @(posedge clk) begin
    if (rst == 0) begin
        for (i = 0; i < NREG; i = i + 1) begin
            breg[i] <= 0;
        end
    end else begin
        if (RegWrite == 0) begin
            breg[addrW] <= datW;
        end
    end
end

endmodule

My problem is that the outputs from BancoRegistro (datOutRa, datOutRb) are needed in the top module for the display to show the information, but that makes it so that they also have to be outputs in the top module. So when I go to the pin planner, I have to set a pin for them which I don’t need. I don’t have any pin to assign to them and when I leave them empty they are automatically set at random, so I get the buzzer making noise and random leds turning on.

I’d like to know if there’s a way to “delete” these unused output nodes or an overall better way to code this so that this isn’t a problem. I’m sorry in advance if I’m doing something dumb, but this was the most “logical” way I came up with and half of the code had already been given by my professor.