when i’m trying to write customized ROM for my project following quartus prime templates advices, i end up with this module :

// Quartus Prime Verilog Template
// Single Port ROM

module memory
#(parameter DATA_WIDTH=256, parameter ADDR_WIDTH=12, parameter OUT_WIDTH=4)
(
    input wire [(ADDR_WIDTH-1):0] addr,
    input wire clk, 
    input wire [7:0] index,
    output reg [(OUT_WIDTH-1):0] q
);

    // Declare the ROM variable
    reg [DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0];

    initial
    begin
        $readmemb("test.txt", rom);
    end
    
    
    always @ (posedge clk)
    begin
        q <= {rom[addr+3][index], rom[addr+2][index], rom[addr+1][index], rom[addr][index]};
    end

endmodule

but unexpectedly, the quartus can’n synthesize and infer the ROM, but also compiles it for very long time then it crashes and gives following message:

and i’m sure that the problem is not from my device, i tried it on different devices

then i tried to simplify the always block for debugging and testing, so i replaced index input with constant number 0, then it worked correctly, with no problems, compile finished in minute, and memory correctly inferred, see the modification :

// Quartus Prime Verilog Template
// Single Port ROM

module memory
#(parameter DATA_WIDTH=256, parameter ADDR_WIDTH=12, parameter OUT_WIDTH=4)
(
    input wire [(ADDR_WIDTH-1):0] addr,
    input wire clk, 
    output reg [(OUT_WIDTH-1):0] q
);

    // Declare the ROM variable
    reg [DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0];

    // Initialize the ROM with $readmemb.  Put the memory contents
    // in the file single_port_rom_init.txt.  Without this file,
    // this design will not compile.

    // See Verilog LRM 1364-2001 Section 17.2.8 for details on the
    // format of this file, or see the "Using $readmemb and $readmemh"
    // template later in this section.

    initial
    begin
        $readmemb("test.txt", rom);
    end
    
    
    always @ (posedge clk)
    begin
        q <= {rom[addr+3][0], rom[addr+2][0], rom[addr+1][0], rom[addr][0]};
    end

endmodule

but i want to use index in my module, cuz i’m reading different bit each time, how?