We are doing a project designing a 5 staged pipelined CPU on RISC-V ISA, when designing the hazard detection unit and forwarding unit, instead of using the common datapath design, we design like this:

• When doing Instruction fetch, fetch 3 instructions instead of one to “peek” if there’s need to forwarding or store.
• Since it would need to fetch three instructions from RAM, at start of a program, it would take 3 cycles to fetch three instructions. Then we store them at three registers. Then next IF stage, we would only need to fetch 1 instruction since the other two are already stored in the register.
• We can decide control signals for the instructions at the decoder and they are passed to the next stage.

We are using FPGA to implement the CPU, I wonder if there are any deficts in this design.