I want to implement the following timing diagram (the numbers here are arbitrary, the main thing is the general principle). In my task a sequence of 4-bit data. This sequence must be written to registers A, B and C and shifted in each corresponding register by 1 clock cycle relative to the previous one.

Here is my code on Verilog:

module shift4bit(clock, data, out, outRegA, outRegB, outRegC);
input clock;
input [3:0] data;
output [3:0] out;
output [3:0] outRegA;
output [3:0] outRegB;
output [3:0] outRegC;
reg [3:0] RegA;
reg [3:0] RegB;
reg [3:0] RegC;

always @(posedge clock) begin
RegA <= data;
RegB <= RegA;
RegC <= RegB;
end

assign out = data;
assign outRegA = RegA;
assign outRegB = RegB;
assign outRegC = RegC;

endmodule

And testbench:

`timescale 1ns / 1ps
module shift4bit_tb; 
// Inputs
reg [3:0] data;
reg clock;
// Outputs
wire [3:0] out;
wire [3:0] outRegA;
wire [3:0] outRegB;
wire [3:0] outRegC;
// Instantiate the Unit Under Test (UUT)
shift4bit uut (.clock(clock),.data(data),.out(out),.outRegA(outRegA),.outRegB(outRegB),.outRegC(outRegB));
initial begin
// Initialize Inputs
data  = 4'b1111;
clock  = 1'b1;
// Wait 100 ns for global reset to finish
#20;
// Add stimulus here
data = 4'b0001; #20;
data = 4'b0010; #20;
data = 4'b0011; #20;
data = 4'b0100; #20;
data = 4'b0101; #20;
data = 4'b0110; #20;
data = 4'b0111; #20;
data = 4'b1000; #20;
end
always #10 clock = ~clock;  
endmodule

I got the following result. The sequence is written to register A, but nothing is displayed in registers B and C, i.e. no shift by 1 clock.