i have a problem where my main code works(i have simulated it in quartus) and the test bench look ok as well, but for some reason when i run the test bench in modelsim the outputs don’t change

this is my main code:

library IEEE;
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity PIC is
port(
    clk             : in std_logic;
    rst_n           : in std_logic;

    wr_n    : in std_logic;
    rd_n        : in std_logic;

    cs_n        : in std_logic;
    inta_n          : in std_logic;

    irq_pic     : out std_logic;
    
    d               : inout std_logic_vector(7 downto 0);
    irq : in std_logic_vector(7 downto 0);
test_irr :out std_logic_vector (7 downto 0); --test
test_prio :out std_logic_vector (7 downto 0);--test
test_mask:out std_logic_vector (7 downto 0); --test
test_irr_en     : out std_logic;
test_msk:out std_logic_vector (7 downto 0) --test
);
end entity PIC;



architecture arc_PIC of PIC is

component cntl is
port(
    wr_n    : in std_logic;
    rd_n        : in std_logic;

    cs_n        : in std_logic;
    irq_pic     : out std_logic;

    irr_en      : out std_logic;
    mask_en     : out std_logic;
    
    d               : inout std_logic_vector(7 downto 0);
    irr         : in std_logic_vector(7 downto 0);
    msk         : out std_logic_vector(7 downto 0)
);
end component;

component ReadReg is
port(
    clk             : in std_logic;
    rst_n           : in std_logic;
    en_n            : in std_logic;
    din             : in std_logic_vector(7 downto 0);
    dout                : out std_logic_vector(7 downto 0)
);
end component;

component MaskReg is
port(
    clk             : in std_logic;
    rst_n           : in std_logic;
    en_n            : in std_logic;
    din             : in std_logic_vector(7 downto 0);
    dout                : out std_logic_vector(7 downto 0)
);
end component;

component Priority_Encoder is
port(
    mask        : in std_logic_vector(7 downto 0);
    irq : in std_logic_vector(7 downto 0);
    prio    : out std_logic_vector(7 downto 0)
);
end component;

---------------------------------

signal prio, msk    : std_logic_vector(d'range);
signal mask, irr: std_logic_vector(d'range);
signal mask_en, irr_en  : std_logic;
signal rst_n_sig : std_logic;

begin

    rst_n_sig <= inta_n AND rst_n;
    u_cntl: cntl
    port map(
        wr_n=> wr_n,
        rd_n    => rd_n,

        cs_n    => cs_n,
        irq_pic => irq_pic,

        irr_en  => irr_en,
        mask_en => mask_en,
        
        d           => d,
        irr     => irr,
        msk     => msk
    );
    
    u_read_reg: ReadReg
    port map(
        clk         => clk,
        rst_n       => rst_n_sig,
        en_n        => irr_en,
        din         => prio,
        dout            => irr
    );
    
    u_msk_reg: MaskReg
    port map(
        clk         => clk,
        rst_n       => rst_n,
        en_n        => mask_en,
        din         => msk,
        dout            => mask
    );
    
    u_prio_enc: Priority_Encoder
    port map(
        mask            => mask,
        irq     => irq,
        prio        => prio
    );

test_irr <= irr;
test_prio<=prio;
test_mask<=mask;
test_msk<=msk;
test_irr_en <= irr_en;
end architecture arc_PIC;

when i simulate the main code in quartus everything is good, but for some reason when i run the test bench in modelsim the outputs don’t change. anyone know what is the problem and how to fix it?
i also tried a few other similar test-benches that were made by other people and it still didn’t work, so i assume it has something to do with the main code, but as i said earlier, when i simulated it in quartus it worked well.
i am new to vhdl and coding in general so please don’t give me a hard time.