I’ve implemented multiple instructions to a RISC-V processor module and I gave instructions to find the greatest common divisor of values 98 and 56, which is 14, and it is stored at the register 16 of the processor. The problem is when i try to show it on the seven segment display of nexys4 ddr board, it only displays a bunch of 0’s. Simulation of the module works just fine, but it does not work when it comes to implementation phase sadly.

Here are the code i wrote. Assume risc-v module is working just fine.

• top_module.v(topR is the risc-v module and top is the module I use for display. final variable is the value the 16th register holds, and the enable signal is true when there is no next instructions to be executed(i.e. 32 bits of X is the Program Counter’s next value.)

module top_module(input clk,input reset,output [7:0] sseg,anode);
    wire[31:0] final;
    wire enable;
    topR topR(clk,reset,sseg,anode,final,enable);
    top top(clk,reset,sseg,anode,final,enable);
endmodule

top.v(display module as stated earlier)

module top(clk, rst, sseg, anode,in,enable);
   input clk, rst,enable;
   input [3:0] in;
   output [7:0] sseg;
   output [7:0] anode;  
   wire [3:0] digit_1, digit_2, digit_3, digit_4;
   wire [7:0] sseg_1, sseg_2, sseg_3, sseg_4;
   wire enable;
   dec_to_binary uut6(clk,rst,in,digit_1,digit_2,digit_3,digit_4);
    scan_unit uut1(
       .clk_s(clk),
       .rst_s(rst),
       .sseg_s({sseg_4, sseg_3, sseg_2, sseg_1}),
       .anode_s(anode),
       .sout_s(sseg),
        .enable_s(enable));
   ssd_decoder_unit uut2(
       .bcd(digit_1),
       .ssd(sseg_1)
   ); 
   ssd_decoder_unit uut3(
       .bcd(digit_2),
       .ssd(sseg_2)
   );
   ssd_decoder_unit uut4(
       .bcd(digit_3),
       .ssd(sseg_3)
   );
   ssd_decoder_unit uut5(
       .bcd(digit_4),
       .ssd(sseg_4)
   );
endmodule

dec_to_binary.v(Expands the digit to convert them to hexadecimal later. I only calculated the least significant four bits because im trying to display the number 14.)

module dec_to_binary(clk,rst,in,digit_1,digit_2,digit_3,digit_4
    );
    input [3:0] in;
    input clk,rst;
    output reg [3:0] digit_1,digit_2,digit_3,digit_4;
    always @(*) begin
        digit_1 = in % 10;
        digit_2 = (in / 10) % 10;
        digit_3 = (in / 100) % 10;
        digit_4 = (in / 1000) % 10;
    end
endmodule

ssd_decoder_unit.v(translates the expanded digits to hexadecimal)

module ssd_decoder_unit(bcd, ssd);
    input [3:0] bcd;
    output reg [7:0] ssd;
    
    // ssd[7] refers to CA
    // ssd[6] refers to CB
    // ssd[5] refers to CC
    // ssd[4] refers to CD
    // ssd[3] refers to CE
    // ssd[2] refers to CF
    // ssd[1] refers to CG
    // ssd[0] refers to DP
    always@(*) begin
        case(bcd)
            4'b0000: ssd[7:0] = 8'h03;
            4'b0001: ssd[7:0] = 8'h9F;
            4'b0010: ssd[7:0] = 8'h25;
            4'b0011: ssd[7:0] = 8'h0D;
            4'b0100: ssd[7:0] = 8'h99;
            4'b0101: ssd[7:0] = 8'h49;
            4'b0110: ssd[7:0] = 8'h41;
            4'b0111: ssd[7:0] = 8'h1F;
            4'b1000: ssd[7:0] = 8'h01;
            4'b1001: ssd[7:0] = 8'h09;
            default: ssd[7:0] = 8'hFF;
        endcase 
    end
endmodule

scan_unit.v(displays each digit on corresponding anode with the help of a counter. This module is the problem i feel but i couldn’t fix it.)

module scan_unit(clk_s, rst_s, sseg_s, anode_s, sout_s,enable_s);
    input clk_s, rst_s,enable_s;
    input [31:0] sseg_s;
    output [7:0] sout_s;
    output [7:0] anode_s;

    reg [7:0] sout_s;
    reg [7:0] anode_s;
    reg [14:0] cntr;
    always @(posedge clk_s) begin
        if(rst_s) begin
            cntr <= 15'd0;
            sout_s <= 8'b11111111;
        end
        else begin // cntr 15-bit sinirdan küçükse arttir
            if(enable_s) begin
                cntr <= cntr + 1;
                if (cntr[14:13] == 2'b11) begin
                    sout_s <= sseg_s[31:24];
                    anode_s<=8'b11110111;
                end
                else if (cntr[14:13] == 2'b10) begin
                    sout_s <= sseg_s[23:16];
                    anode_s<=8'b11111011;
                end
                else if (cntr[14:13]== 2'b01) begin
                    sout_s <= sseg_s[15:8];
                    anode_s<=8'b11111101;
                end
                else if (cntr[14:13] == 2'b00) begin
                    sout_s <= sseg_s[7:0];
                    anode_s<=8'b11111110;
                end
                else begin
                    sout_s <= sout_s;
                    anode_s <= 8'b11111111;
                end
            end
        end
   end
endmodule

top_module.ucf

## Clock signal
NET "clk"   LOC=E3  | IOSTANDARD=LVCMOS33;                  #Bank = 35, Pin name = #IO_L12P_T1_MRCC_35,                 Sch name = clk100mhz

## Switches
NET "reset"          LOC=L16 | IOSTANDARD=LVCMOS33; #IO_L3N_T0_DQS_EMCCLK_14

## 7 segment display
NET "sseg<7>"             LOC=T10 | IOSTANDARD=LVCMOS33; #IO_L24N_T3_A00_D16_14
NET "sseg<6>"             LOC=R10 | IOSTANDARD=LVCMOS33; #IO_25_14
NET "sseg<5>"             LOC=K16 | IOSTANDARD=LVCMOS33; #IO_25_15
NET "sseg<4>"             LOC=K13 | IOSTANDARD=LVCMOS33; #IO_L17P_T2_A26_15
NET "sseg<3>"             LOC=P15 | IOSTANDARD=LVCMOS33; #IO_L13P_T2_MRCC_14
NET "sseg<2>"             LOC=T11 | IOSTANDARD=LVCMOS33; #IO_L19P_T3_A10_D26_14
NET "sseg<1>"             LOC=L18 | IOSTANDARD=LVCMOS33; #IO_L4P_T0_D04_14
NET "sseg<0>"             LOC=H15 | IOSTANDARD=LVCMOS33; #IO_L19N_T3_A21_VREF_15

NET "anode<0>"          LOC=J17 | IOSTANDARD=LVCMOS33; #IO_L23P_T3_FOE_B_15
NET "anode<1>"          LOC=J18 | IOSTANDARD=LVCMOS33; #IO_L23N_T3_FWE_B_15
NET "anode<2>"          LOC=T9 | IOSTANDARD=LVCMOS33; #IO_L24P_T3_A01_D17_14
NET "anode<3>"          LOC=J14 | IOSTANDARD=LVCMOS33; #IO_L19P_T3_A22_15
NET "anode<4>"          LOC=P14 | IOSTANDARD=LVCMOS33; #IO_L8N_T1_D12_14
NET "anode<5>"          LOC=T14 | IOSTANDARD=LVCMOS33; #IO_L14P_T2_SRCC_14
NET "anode<6>"          LOC=K2 | IOSTANDARD=LVCMOS33; #IO_L23P_T3_35
NET "anode<7>"          LOC=U13 | IOSTANDARD=LVCMOS33; #IO_L23N_T3_A02_D18_14