The book “Computer Architecture”, by Hennessy/Patterson, 6th ed, on page 394, includes an example with true sharing and false sharing misses.

here is the example

It says that initially (before time stamp #1), “Assume that words z1 and z2 are in the same cache block, which is in the shared state in the caches of both P1 and P2.”

I assume the underlaying coherence protocol assumed for this example is MSI.

My question: why in time stamp #1 we have a true sharing miss and not true sharing hit ? why moving from Shared to Modified in MSI requires write miss for processor P1 (that wants to write to Z1) and not just hit + invalidation on the bus to invalidate all other possible copies of the same cache line of Z1)?

I don’t see a reason to have a write-miss and flush the value of this cache line (with Z1 and Z2) to main memory if the cache state is already Shared (meaning has the same value in the cache and in the main memory).