I am working on an assignment to implement a 6-time folded FIR filter in Verilog. Both the filter module and the stimulus file compile without issues, but when I start the simulation, I get an error message saying “Modelsim is exiting with code 7” and “error loading design.” How can I resolve this issue?

module FIR_filter_folded_memory(
    input clk10, clk60, rstn,
    input [13:0] c0, c1, c2, c3, c4, c5
);

reg [7:0] counter1;
reg [10:0] counter2;
reg [2:0] counter_MAC;
reg NCE_I;
reg NCE_O;
reg [7:0] ADDR_O;
reg [2:0] out_counter;
wire [5:0] RA_I, RA_O;
wire [1:0] CA_I, CA_O;
wire NWRT_I;
wire NWRT_O;
wire [15:0] out_mem, D0, D1, D2, D3, D4, D5;
wire [25:0] out_fil;
wire [2:0] sel0, sel1;
wire sel2, sel3;

always @ (posedge clk10) begin
    if(!rstn) counter1 <=8'b0;
    else if(!NCE_I) counter1 <= counter1 + 1;
    else counter1 <= counter1;
end

always @ (posedge clk10) begin
    if(!rstn) NCE_I <= 1'b1;
    else NCE_I <= 1'b0;
end

always @ (posedge clk60) begin
    if(!rstn) counter2 <=11'b0;
    else if(!NCE_I) counter2 <= counter2 + 1;
    else counter2 <= counter2;
end

always @ (posedge clk60) begin
    if (!rstn) begin
        counter_MAC <= 3'b0;
    end else if (!NCE_I) begin
        if (counter_MAC < 5) begin
            counter_MAC <= counter_MAC + 1;
        end else if (counter_MAC == 5) begin
            counter_MAC <= 3'b0;
        end else begin
            counter_MAC <= counter_MAC;
        end
    end else begin
        counter_MAC <= counter_MAC; 
    end
end

always @(posedge clk60) begin
    if (!rstn) begin
        ADDR_O <= 0;
        out_counter <= 0;
    end else if (counter2 < 44) begin
        ADDR_O <= 0;
        out_counter <= 0;
    end else if (counter2 >= 44) begin
        if (out_counter < 5) begin
            out_counter <= out_counter + 1; 
        end else begin
            out_counter <= 0; 

            if (ADDR_O < 255) begin
                ADDR_O <= ADDR_O + 1;
            end else begin
                ADDR_O <= ADDR_O; 
            end
        end
    end
end

assign sel0 = counter_MAC;
assign sel1 = counter_MAC;
assign sel2 = (counter_MAC == 1);
assign sel3 = (counter_MAC == 1);


assign NWRT_I = 1'b1;
assign {RA_I, CA_I} = counter1[7:0];
assign NWRT_O = ~((counter2 > 43) && (out_counter == 0));
assign NCE_O = ~((counter2 > 43) && (out_counter == 0));
assign {RA_O, CA_O} = ADDR_O[7:0];



rflp256x16mx2 FOLDED_INPUT_MEM(NWRT_I, 16'b0, RA_I, CA_I, NCE_I, clk10, out_mem);

ff_16bit ff0(D0, out_mem, clk10, rstn);
ff_16bit ff1(D1, D0, clk10, rstn);
ff_16bit ff2(D2, D1, clk10, rstn);
ff_16bit ff3(D3, D2, clk10, rstn);
ff_16bit ff4(D4, D3, clk10, rstn);
ff_16bit ff5(D5, D4, clk10, rstn);

filter filter0(out_fil, D0, D1, D2, D3, D4, D5, c0, c1, c2, c3, c4, c5, sel0, sel1, sel2, sel3, clk60, rstn);

rflp256x26mx2 FOLDED_OUTPUT_MEM(NWRT_O, out_fil, RA_O, CA_O, NCE_O, clk60, 26'b0);


endmodule

`timescale 1ns/10ps
module sti_folded_FIR;

    wire    [13:0] c0 = 14'h3aa4 ;
    wire    [13:0] c1 = 14'h1433 ;
    wire    [13:0] c2 = 14'he37  ;
    wire    [13:0] c3 = 14'h1a57 ;
    wire    [13:0] c4 = 14'h917  ;
    wire    [13:0] c5 = 14'h2c1d ;

    reg clk10;  // 100MHz : 10ns
    reg clk60;  // 16.67MHz : 60ns
    reg rstn;

    reg [25:0] sig_mat [0:255];
    reg [25:0] out_mat;
    reg [25:0] FOLD_OUT;
    
    FIR_filter_folded_memory FIR(.c0(c0), .c1(c1), .c2(c2), .c3(c3), .c4(c4), .c5(c5), .clk10(clk10), .clk60(clk60), .rstn(rstn));
    
    initial begin
        clk10 = 1;
        clk60 = 1;
        rstn = 0;
        #10
        rstn = 1;
    end
    
    always #5 clk10 = ~clk10;
    always #30 clk60 = ~clk60;
    
    initial begin
        $readmemh("input_vector_hex.txt", FIR.FOLDED_INPUT_MEM.array); // Check the path of memory location (module instance)
    end

    integer i = 0;    
    integer err = 0;
    initial begin        
        $readmemh("output_vector_hex.txt", sig_mat);
        wait(rstn == 1'b1);
        #600;  // Change if you need
        for (i = 0; i < 256; i = i + 1) begin
            out_mat = sig_mat[i];
            FOLD_OUT = FIR.FOLDED_OUTPUT_MEM.array[i]; // Non-blocking assignment removed
            #60;
            if (FOLD_OUT != out_mat) err = err + 1;
        end
        $stop;
    end

endmodule

I have uploaded each code.

checking about port