I am developing a control system in simulink that takes in the data from external ADC and executes the control model based on the data. My goal is to use FPGA and the project consists of 2 blocks, 1) ADC acquisition block and 2) Control algorithm block. I completed the control algorithm (fixed point) and everything works fine in simulation. Now in real world, i need to interface to external ADC (AD7606 simultaneous sample), collect 4 channels of data and then feed the control algorithm to get the desired output. Control algorithm runs at 20KHz.
I am facing some difficulty in fixing appropriate sampling time and method of synchronization between the two blocks. ADC acquisition block has to generate bunch of interface signals to ADC and subsequently store the acquired signals in a latch before feeding to the control block.
My questions is, a) how do I fix the sampling time of adc acquisition block? (the external clock to FPGA is 1 MHz)
b)How to ensure that the acquired data is stable before control model executes them seamlessly?
c) It is obvious that the two blocks run at different data rates. How do I configure simulink for multirate problem so as to effectively generate hdl code?
Control Algorithm was designed and simulated. Unable to model the ADC acquisition block with different sample time
Vishnu is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.