As shown below, the two memory outputs (TRAN_out, DIRE_out) are 0 output for two clock cycles, and then the x output is output for seven cycles before the desired output comes out. Please let me know we have to modify in the top module or in the stimulus file so that the desired output comes out immediately(i will upload the top module separtely because it can be too long) without
0 unlike i uploaded. out_mat has to come out with TRAN_out and DIRE_out at the same time
simulation result
` module sti_FIR_filter;
reg clk, reset;
reg [25:0] sig_mat [0:255];
reg [25:0] out_mat;
reg [25:0] TRAN_out;
reg [25:0] DIRE_out;
wire [13:0] c0 = 14'h3aa4 ;
wire [13:0] c1 = 14'h1433;
wire [13:0] c2 = 14'he37;
wire [13:0] c3 = 14'h1a57;
wire [13:0] c4 = 14'h917;
wire [13:0] c5 = 14'h2c1d;
top_FIR_filter FIR(clk, reset, c0, c1, c2, c3, c4, c5 );
initial
begin
clk = 1;
reset = 0;
#10
reset = 1;
end
always #5 clk = ~clk;
initial $readmemh("input_vector_hex.txt", FIR.DIRECT_INPUT_MEM.array);
initial $readmemh("input_vector_hex.txt", FIR.TRANS_INPUT_MEM.array);
integer i=0;
initial
begin
$readmemh("output_vector_hex.txt", sig_mat);
#(110);
for (i=0; i<256; i=i+1)
begin
out_mat <= sig_mat[i];
TRAN_out = FIR.DIRECT_OUTPUT_MEM.array[i];
DIRE_out = FIR.TRANS_OUTPUT_MEM.array[i];
if((TRAN_out != out_mat) || (DIRE_out != out_mat)) err = err + 1;
#(10);
end
$stop;
end
endmodule`
i tried to modify the delay between for statement and outside of that but it didn’t work.
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