Im working on a Verilog switch matrix using a Cyclone V DE10 Nano developer board, and I have an issue where a couple multiplexer modules I made are working, where a couple aren’t when given the same control signals. I was wondering if anyone could help me point out where its broken.

Below is my top-level module. The uart_receiver module receive a UART signal, and passes it to its 8bit register output to control_sig. The uart_decoder module takes this in, and decodes the input channel from the message and passes that to each mux. The multiplexers also receive enable and load signals from the decoder which are time delayed. these signals are on 8bit wires that all correspond to specific multiplexers.

module SwitchMatrix(di, ci, do, co, clk_50, reset_uart,
                            rx, LED);

input       [7:0] di, ci;
input       clk_50;
input       rx, reset_uart;
output  [7:0] do, co;
output reg   [7:0] LED;

wire        [7:0] control_sig;

    always @(control_sig) begin
        LED = control_sig;
    end

    uart_receiver uart_rx(.clk_50MHz(clk_50), .reset(reset_uart), .rx(rx), .LED(control_sig));

    //switch_8x8x2 switch_matrix(.clk(clk_50), .uart_data(control_sig), .data_in(di), .clk_in(ci), .data_out(do), .clk_out(co), .LED());
    
    wire [2:0] in_channel;
    wire [7:0] load, enable;

    uart_decoder decode(.uart_data(control_sig), .clk(clk_50), .in_channel(in_channel), .out_channel(), .load(load), .enable(enable), .LED());

    mux_8to1 clk_mux0(.data(ci), .ctrls(in_channel), .load(load[0]), .enable(enable[0]), .data_out(co[0]));
    mux_8to1 clk_mux1(.data(ci), .ctrls(in_channel), .load(load[1]), .enable(enable[1]), .data_out(co[1]));
    mux_8to1 clk_mux2(.data(ci), .ctrls(in_channel), .load(load[2]), .enable(enable[2]), .data_out(co[2]));
    mux_8to1 clk_mux3(.data(ci), .ctrls(in_channel), .load(load[3]), .enable(enable[3]), .data_out(co[3]));
    mux_8to1 clk_mux4(.data(ci), .ctrls(in_channel), .load(load[4]), .enable(enable[4]), .data_out(co[4]));
    mux_8to1 clk_mux5(.data(ci), .ctrls(in_channel), .load(load[5]), .enable(enable[5]), .data_out(co[5]));
    mux_8to1 clk_mux6(.data(ci), .ctrls(in_channel), .load(load[6]), .enable(enable[6]), .data_out(co[6]));
    mux_8to1 clk_mux7(.data(ci), .ctrls(in_channel), .load(load[7]), .enable(enable[7]), .data_out(co[7]));
    
    mux_8to1 dat_mux0(.data(di), .ctrls(in_channel), .load(load[0]), .enable(enable[0]), .data_out(do[0]));
    mux_8to1 dat_mux1(.data(di), .ctrls(in_channel), .load(load[1]), .enable(enable[1]), .data_out(do[1]));
    mux_8to1 dat_mux2(.data(di), .ctrls(in_channel), .load(load[2]), .enable(enable[2]), .data_out(do[2]));
    mux_8to1 dat_mux3(.data(di), .ctrls(in_channel), .load(load[3]), .enable(enable[3]), .data_out(do[3]));
    mux_8to1 dat_mux4(.data(di), .ctrls(in_channel), .load(load[4]), .enable(enable[4]), .data_out(do[4]));
    mux_8to1 dat_mux5(.data(di), .ctrls(in_channel), .load(load[5]), .enable(enable[5]), .data_out(do[5]));
    mux_8to1 dat_mux6(.data(di), .ctrls(in_channel), .load(load[6]), .enable(enable[6]), .data_out(do[6]));
    mux_8to1 dat_mux7(.data(di), .ctrls(in_channel), .load(load[7]), .enable(enable[7]), .data_out(do[7]));


endmodule

The problem I am encountering is that all of the multiplexers that are connected to the do outputs refuse to switch. Connecting di to co works, as well as ci to ci. I can’t figure out why this doesn’t work as they are utilizing the exact same logic with the same control signals.