I am a fpga (verilog) newbie, I wrote a piece of code, the simulation can be passed, but I’m not sure if this can really be achieved in reality (I have not bought the FPGA chip, after all, it is very expensive), please big brother take the time to point out the newbie, so that I can further study!
Thank you so much to all the dudes and dudettes around the world.picture

Like it says above,to can further study!

module spi_control (
    //total cmd - spi
    input i_clk,
    input [7:0] i_data,
    input i_rst,
    input i_send,

    //spi-adc:
    input i_MISO,
    output reg o_cs = 1,
    output reg o_sclk = 0,
    output reg o_MOSI = 1,

    //spi - sdram
    output reg [23:0] o_MISOData = 24'b0
    
);
    // reg [23:0] o_MISOData = 24'b0 ;
    //for o_sclk :
    reg [3:0] r_mosi_cnt8 = 0;
    wire w_starCnt16 = ~o_cs;
    wire w_Sclk = r_mosi_cnt8[2];
    reg [3:0] r_shift8 = 0 ;
    wire w_posedegeSclk; assign w_posedegeSclk = (r_mosi_cnt8[2:0] == 3'b100) ? 1 : 0 ;
    always @(posedge i_clk) begin
        if (w_starCnt16) begin
            r_mosi_cnt8 <= r_mosi_cnt8 + 1 ;
        end else if (r_mosi_cnt8 == 8) begin
            r_mosi_cnt8 <= 0 ;
        end
    end
    //三个状态：00空闲、01写、10读
    parameter IDLE = 2'b00;
    parameter WRITE = 2'b01;
    parameter READ = 2'b10;
    reg [1:0] state  = 2'b00;
    //for state 转换：
    always @(posedge i_clk) begin
        if (~i_rst) begin
            o_sclk  <= 0    ;
            o_MOSI  <= 1    ;
            state   <= IDLE ;
        end
        else case (state)
            IDLE: begin
                o_sclk  <= 0    ;
                o_MOSI  <= 1    ;
                if (~i_send) state <= WRITE;
            end
            WRITE:begin
                o_cs    <= 0    ;//同时会启动o_sclk，在上面的for o_sclk 代码中
                o_sclk  <= w_Sclk ;
                if (w_posedegeSclk) begin //sclk上升沿时候发送数据
                    o_MOSI <= i_data[7 - r_shift8];
                    r_shift8 <= r_shift8 + 1 ;
                    if (r_shift8 == 8) begin //发送8个
                        state    <= READ ;
                        r_shift8 <= 0    ;
                        o_MOSI   <= 1    ;
                    end
                end
            end
            READ:begin
                o_sclk  <= w_Sclk ;
                if (w_posedegeSclk) begin //sclk上升沿时候发送数据
                    o_MISOData[7 - r_shift8] <= i_MISO ; //这里的数据是一位一位的发送给sdram的,实际需要全部接收完一起发24bit,
                    r_shift8 <= r_shift8 + 1 ;           //然后要加一个命令判断,如果是连续读这里不一样shift
                    if (r_shift8 == 8) begin
                        state       <= IDLE ;
                        r_shift8    <= 0    ;
                        o_cs        <= 1    ;
                        o_sclk      <= 0    ;//计数器清零会有延迟,这里提前清零
                        //r_mosi_cnt8 <= 0    ;//计数器清零会有延迟,这里提前清零
                    end
                end
            end
            default: ;
        endcase
    end


endmodule