I use this HLS code to generate an IP core and bundle port:

void mnist_nn_predict(float* input, float* output) {
    #pragma HLS INTERFACE s_axilite port=return bundle=CRTL_BUS   
    #pragma HLS INTERFACE m_axi port=input offset=slave bundle=gmem0  
    #pragma HLS INTERFACE m_axi port=output offset=slave bundle=gmem1  

    for (int i = 0; i < n; i++) {
        output[i] = input[i];  // simple example
    }
    return;
}

then I design the block like this:
enter image description here

then auto match address:
enter image description here

I Hope Bram0 for store data from PS. IP can read from Bram0 and write in Bram1.

But why there are 2 address for IP input and output Bus, I think there should be only one fixed address for IP to read and write.

SO how I can control the IP data stream as i thought, do I need to modify my block design?