Cacheline size usually is 64 bytes, DDR data line bit width is 64 bits and burst length is 8, a burst transaction is 64 bytes which is equal to cacheline size.
But if cacheline size is 128bytes or 256bytes, What happens to DDR when cacheline miss.
If cacheline size is 128bytes, DDR will split this read request into two request or send a burst of length is 16?
DDR prefetch is 8n, its burst length is 8, I don’t know if it support burst length is 16.
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